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| xr68c681 features !" # $ $ % %& ' % ' ( $ %( )$ *++ $ ' ( " *++ $ %( , - *(% ( ./ *( # ' % # *( 0 % ( 1 (++ *( % # $ $ *( '( + 2' %( $ ' ( 2! '3 ((& !( *( 4 5 '3 .%" /5 '3 67.% 8 " 29" : ' :,* 7 $ :,* 7 $ % ( + '( / *( .( # ( 2(- %3 # $(( % # ; ' '3 $- < 0 , % % / 0 , % # % ( - + % ' % # % ' ( %'( + &% $& $ $' ( - , ( ( /$ (- (' /' $ : , ' -& applications ( $( &% % ( , ., ( 2 + $ ('( &% % general description 25 ( % %& ' % ' ( $ %( (% $ ' ('( % $ (' ($ % +& ( $ $ + $ ! %& ' % ' ('( % ' % ( %( - '3- (% $ %(- $ + % ( (' ' %% % $ %&% % $ & % $ ( $ ( $ ( ( 5/</< $ (' ++ % %( - # % ( + /< +(& + (' ' %% % (% + (' $ %( - $ ' $ & " ( (- + ' $ %(& 2,#. < ' %% ($ (- + ' $ ' %( " $ (% '3- $ ( = ( #, == ( ,: ordering information part no. pin package operating temperature range 5/</<> == ,: ?@ 5/</<> == ,: = ?<6 part no. pin package operating temperature range 5/</<8 = #, = ?<6 5/</<, = ,#, ?@ 5/</<, = ,#, = ?<6 xr68c681 .a figure 1. block diagram of the xr68c681 duart device $$ %% ' $ $ ' $ * ( # # # # #; %'( * *( 0 .( (( - *% *++ # *% @ = 7 22 # 7 #8 5.:7 5 - + ' % #, #, # , #, #,6 9 9 $ -(% % % -(% * 5* 5* 9 9 $ -(% % % -(% 5 5 , , '( ' : -(' , , , ,@ ( $(' % 8 ' ( #: <<1 , $' xr68c681 1 pin configuration #,1 1 #, = 1 = #, .a8 78 5* 5* , ,1 ,6 1 = 6 / @ < 40 pin pdip, cdip (0.600?) 6 / @ < ,@ 1 6 @ 08 '' #,= #,6 # 7 #, 22 5 5.:7 5 5 , , ,= ,/ = / #8 < @ / 6 = 1 1 1 1 11 1= 16 1/ 1@ 1< 1 = xr68c681cj 22 5 5.:7 5 8 5 , , ,= ,6 ,1 , 5* 8 5* :7 .a #, = 44 pin plcc ,@ ,/ 1 #, #,1 8 ;'' #,= #,6 # 7 #, 1 6 @ 08 8 #8b = / 1 1< 1@ 1/ 16 1= 11 1 1 1 @ < 1 = 6 / @ < 1 = 6 / @ < 1 = 6 / == =1 = = = xr68c681 pin description pin number (44 pin plcc) pin number (40 pin dip) symbol type description 8 no connect. # lsb of address input. (% ( " - ( $$ %% ( %" = % $ % ' ' ( -(% % ( ( $ (' $ ( - $ $ ( ( % ( , 1 #,1 5 # input port 3. 0 % ( ! ' '3 ( + %( 5 = 1 # address input. 6 = #, * # input port 1. 0 % ( (% ( ' ' +(- $ '( * $ # * / 6 1 # address input. @ / = # msb of address input. (% ( " - ( $$ %% # %" 1 % $ % ' ' ( -(% % ( ( $ (' xr68c681 = pin description (cont?d) pin number (44 pin plcc) pin number (40 pin dip) symbol type description < @ #, # input port 0. 0 % ( (% ( ' % ' +(- $ '( ' $ # < .a # read/write input. #+ (% ( (% (- ( (% " , (% + ( - 2 '&' ( #+ (% ( (% " ( (% " , (% + ( - a#2 '&' ( 7 data transfer acknowledge. " '( 4 %% % 7 ( $ ( + , % 2 a#2 ( (% & ' /< +(& + , % c( % (% %(- + (% ( $ (' %" ( $ c('3& $ & ' 2 a#2 '&' #+ %% % 7 $ ( - 2 ( " ( ( $( ' % , c % $ $ (% $ % #+ 7 (% %% $ $ ( - # '3 $- '&' " (% ( + ( - , ' % + #; # ; ' -(% ( $ % #+ %% % 7 $ ( - a#2 '&' " ( (% ( + ( - , $" $ %" % ' $ ( $ % ++ + $ (' 5* # receiver serial data input- channel b. % %(- (+(' ( + ' ' (% ' ( $ +( % #+ ! ' ( ' '3 (% % '(+( $" ' ( $ $ (% % $ (%( - $- + (% ' '3 8 no connect. 1 5* transmitter serial data output - channel b. % %(- (+ (' ( + ' (% %( $ +( % (% (% $ ( 3( - (- % %( (% ($ " $(% $" ( - ( ' :,* 7 $ #+ ! ' '3 (% % '(+( $" %( $ $ (% % (+ $ + %( (+ -(% +( - $- + (% ' '3 = , * output 1. - % (% ' % ' +(- $ % '( ' * c % $ * 6 1 ,1 5* 5* .de output 3. - % (% ( ' % ' +(- $ ' * %( 5 '3 5*" ' * ' ( 5 '3 5*" % '( " $ ( .( $& .de / = ,6 5e. ::d* output 5. - % (% ( ' % ' +(- $ $ ( " '( ' * 5e. :: " '( xr68c681 6 pin description (cont?d) pin number (44 pin plcc) pin number (40 pin dip) symbol type description @ 6 ,@ 5ed output 7. - % (% ( ' % ' +(- $ $ ( '( ' 5e < / #. three state data bus. @ 1 #. three state data bus. < 6 #. three state data bus. @ #. msb of eight bit three state data bus. %+ % , $ 3 ' $ % ' %(%% + ( % @ % (% % $ ( (% (- " !' $ ( - # 7 '&' 08 ground. + ' 1 8 no connect. = #8 interrupt request. '( : " ( #8 (% %% $ '' ' + + ' (f% %3 ( ( - ' $(( % (% %(- ( ( %% $ - ( % (' ( $ ( - $ ' ' $(( % '%( - ( c % % (( $ 6 / #. three state data bus. / 1 = #. three state data bus. @ = #. three state data bus. < 6 #. lsb of the eight bit three state data bus. %+ % , $ ) 3 ' (% % % (% % $ ( (% (- " !' $ ( - # 7 '&' / ,/ 5ed output 6. - % (% ( ' % ' +(- $ '( " $ ( ' 5e 5ed 1 @ ,= 5e. ::d output 4. - % (% ( ' % ' +(- $ $ ( ' 5e. :: '( 1 < , 5 d5 5 d/5 output 2. - % (% ( ' % ' +(- $ ( 5 /5 ' '3 + ' %( 1 , output 0. - % (% ( ' % ' +(- $ '( c % $ xr68c681 / pin description (cont?d) pin number (44 pin plcc) pin number (40 pin dip) symbol type description 11 1 5 transmitter serial data output. % %(- (+ (' ( (% %( $ +( % (% (% $ ( 3( - (- % %( (% ($ " $(% $" ( - ( ' :,* 7 $ #+ ! ' '3 (% % '(+( $" %( $ $ (% % (+ $ + %( (+ -(% +( - $- + ' '3 1= 8 no connect. 16 1 5 # receiver serial data input. % %(- (+(' ( (% ' ( $ +( % #+ ! ' ( ' '3 (% % '(+( $" ' ( $ $ (% % $ (%( - $- + ' '3 1/ 1 5.:7 # crystal output or external clock input. (% ( (% ' '( + %($ + ' &% $ ''( - $ ( %'( (% % $ #+ %'( (% % $" ! ' '3 %(- % %( $ (% ( # $ + 5/</< $ (' + '( &" % % %& %(- ( + c '( % 9g $ = 9g (% c( ' & ( ' &% %'( & ! : ' ( ' '3 %(- 1@ 11 5 # crystal input. '( + %($ + ' &% %( + 5.:7 #+ %'( (% % $" ''( % % ' ' $ + (% ( - $ (% ( % + (+ ! ' '3 (% %( $ 5.:7 1< 1= 22 # master reset. (% ( ' % ( -(% % " *" #" #" ," ," ( (((g % #; / " % % .( " ' % ( %" , ,@ ( -(' h (- i % " $ ' % % ( ' % ( ( '( % ( 5 $ 5* 3( - (- 1 16 # chip select. '( $ % (% % $ (% (- %+ % , $ ( @ $ (% = 1/ #, .d25 5* # input 2. 0 % ( (% ( ' % ' +(- $ . ! ' '3 ( " ' * ' ( '3 # 5* = 1@ # 7 # interrupt acknowledge. '( : (% ( (% , f% % % ( c % (%% $ & $ (' a , %% % (% ( " ( ( $(' % f% ( c % (% % (' $" $ & ! % '&' ( ( '3 $- '&' ( % $ , f% ( '3 $- & '( - ' % + # ; ' -(% #; $ % @ xr68c681 @ pin description (cont?d) pin number (44 pin plcc) pin number (40 pin dip) symbol type description = 1< #,6 5* # input 5. 0 % ( (% ( ' % ' +(- $ % ' * %( ! ' '3 ( 5* =1 1 #,= 5 # input 4. 0 % ( (% ( ' % ' +(- $ % ' ' ( 2! '3 # 5 == = ; xr68c681 < dc electrical characteristics 1, 2, 3 test conditions: t a =0-70 c, v cc =5v+ 5% unless otherwise specified. symbol parameter min typ max unit conditions ; #: # : ; - 6 < ; ; #9 # 9(- ; - ; ; ; #9 # 9(- ; - (( & ; j 66 6 ;#95 # 9(- ; - 5.:7 = ; ; ; : : ; - = ; # : j = ; 9 9(- ; - = ; # 9 j = # #: # : 3- 6 6 ; #8 j ; # #:2: ' ,( : 3- 1 ?1 ; #8 j ; # 5: 5 # : ; #8 j # 5: 5 # : @ # 5#9 5 # 9(- ; #8 j; # 59 5 # 9(- ; #8 j; # :: % ( : 3- ; j ; # ( : 3- ; j ; # , & = / 6 '( $ # , & = 1 $& $ notes 1. parameters are valid over the specified temperature and operating supply ranges. typical values are 25 c, v cc = 5v and typical processing parameters. 2. all voltages are referenced to ground (gnd). for testing, input signal levels are 0.4v and 2.4v with a transition time of 20ns maximum. all time measurements are referenced at input voltages of 0.8v and 2.0v as appropriate. see figure 31. 3. for prime grade n, p, j, l, m, ml, v cc =5v+ 10% 4. measured operating with a 3.6864mhz crystal and with all outputs open. xr68c681 ac electrical characteristics 1, 2, 3 test conditions: t a =0-70 c, v cc =5.0v + 5% unless otherwise specified. symbol parameter min typ max unit conditions rest timing (see figure 32 ) 2 22 ,% a($ % read, write and interrupt cycle timing ( figure 33, figure 34, figure 35 ) = ( : % 9 = 9 $ ( + 9(- % a .a ( : % a9 .a ( + 9(- % a 9(- ,% a($ =" 6 % # 7 9(- + 7 : % ;($ + # 7 : / @6 % *% ( - + # 7 9(- % ( : % 9 9 $ ( + : 6 % : 7 : + $ ;($ % 9 7 9(- + # 7 9(- % 7 9(- # $ ' + # 7 9(- 6 % # 7 % ( h9(- i @ < % port timing ( figure 36 ) , , # ( : .a 9(- % ,9 , # 9 $ ( + 9(- % , , ;($ + .a " 9(- = % interrupt output timing ( figure 37 ) # #8 ,1 ,@ % $ % # % 9(- + 4 + # % % *(% ( # #, + # %3 ( # 1 1 % % clock timing ( figure 38 ) :7 5.:7 2! 9(- : ( % :7 5.:7 &% 2! c '& 1/<= @1@ 9g .( 2! '3 9(- : ( #, % .( 2! '3 c '& @1@ 9g xr68c681 ac electrical characteristics 1, 2, 3 (cont?d) test conditions: t a =0-70 c, v cc =5.0v + 5% unless otherwise specified. symbol parameter min typ max unit conditions clock timing ( figure 38 ) 5 5 $ 5 2! 9(- : ( < % + 5 5 $ 5 2! c '& /5 / 9g 5 9g transmitter timing ( figure 39 ) 5 5 & 5 2! : 16 % 5 & 5 # : 6 % receiver timing ( figure 40 ) 5 5 ( 5 2! 9(- = % 59 5 9 $ ( + 5 2! 9(- % notes 1. parameters are valid over the specified temperature and operating supply ranges. typical values are 25 c, v cc = 5v and typical processing parameters. 2. all voltages are referenced to ground (gnd). for testing, input signal levels are 0.4v and 2.4v with a transition time of 20ns maximum. all time measurements are referenced at input voltages of 0.8v and 2.0v as appropriate. see figure 31. 3. ac test conditions for outputs: cl = 50pf, rl = 2.7k to v cc . 4. consecutive write operations to the same register require at least three edges of the x1 clock between writes. 5. this specification imposes a 6 mhz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous read or write cycle. a higher 68000 clock can be used if this is not the case. 6. this specification imposes a lower bound on cs and iack low, guaranteeing that they will be low for at least one clk period. 7. this parameter is specified only to insure dtack is asserted with respect to the rising edge of x1/clk as shown in the timing dia- gram, not to guarantee operation of the part. if the specified setup time is violated, dtack may be asserted as shown or may be asserted one clock cycle later. 8. the minimum high time must be at least 1.5 times the x1/clk period and the minimum low time must be at least equal to the x1/clk period if either channel?s receiver is operating in external 1x clock mode. specifications are subject to change without notice absolute maximum ratings 1 & ; - @; - /6 6 ; - % ( % ' 0 $ 6; ?@; 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rat- ing only, and functional operation of the device at these or any other conditions above those indicated in the ?electrical characteris- tics? section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. this product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive stat- ic charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated maximum. xr68c681 system description 5/</< ' %(%% + ( $ $ " + $ ! ' ('( ' %k ' ' %(%( - + ( %( $ ' ( 2' ' + & ( $ $ & - $ + ( - $ $ $ + (% $ %(- $ ( +' ( /< (& + (' ' %% % ( ( ( ! ' % ( - % $ + ' ' ( $ %( & % ' $ + + 1 ( & - $ +(! $ ( %" + ' '3 $ ( $ + ( .( " + ! & %( $ ! /! ' '3 ( - % ' + 1 $(++ +(! $ ( % ' $( '& + ' &% ' ' $ ' %% ( % + ! ' '3 ((& ( $ $ & - ( - % $ + ' ( $ %( + ' ' 3 % '( + %( % $ ' ('( % %' % '% $ ( %&% % ' ( $ (% c$ $ ++ $ $ %( $ (% $ ++ $ ( ' ( # % ( $ ( ((g (%3 + ' ( $ $' $ ( ( $ ( ('( % % ($ % + ' '((& ( (( %(%%( + $ (' ++ + ' (( - (% +" % ( - %% + $ % ($ % - % / ( .( (' & % % $ % - ( - %" ( % / ( ( $ ( % < ( % principles of operation figure 1 % % '3 $(- + /</< % (% $ ( '3 $(- " ' %(%% + + ( - l + '( '3%4 *% *++ # # , ( ('( % % $ * ( (( - , a. data bus buffer $ % ++ ($ % ( +' ( ( ( ' ( $ ! $ % % # (% ' $ & ( ' '3 $ %+ % 3 ' % , $ b. operation control block ' -(' + ( ' '3 ' ( % ( - ' $% + , $ - % %(- % ( % % '( % + ( ' '3 + '( % % % ( +' % + $ (' '(+('&" ( (% % %( + -(% $$ %% $ ' $( -" $ ' $ $ ' $( - + ' $% % $ %" (&" ' ('( ' %" % % .( $( - h%% -(% i ( $ ' ('( + ' ' %% $ ( ( ' '3 ( ' '3 ( ' + ' % $ + ( - ( %(- %4 $$ %% -(% ' (%4 = .a # # 22 ( '$ % %+ '3 $- 7 (' (% %% $ $ ( - $ %+ '&' % ( $ ( + , c % $ ( % ' $ %% $ 7 %(- ( $(' %" , " ( $ % ' $" & $ % ++ " $ ( - ( '&' k c % $ $ + (% $ % $ (% ($ $ ( - $ '&' " ( ' (% $ % $ ( - ( '3 $- '&' a %( - /< +(& ' %% " 5 <</< $ % ++ % $ % $ ( ( + (% $ (' ( + ( ( +' /< (& , ' %% 5 <</< $ (' " % % 5 <</< $ % b.1 duart register addressing $$ %%( - + ( -(% % + (% % $ ( table 1 , % % + -(% % h $ &i $ % ha ( &i 2' ' (% ($ $ ( + ( - $ $(' $ $$ %% -(% % xr68c681 $ -(% $ -(% % $ % -(% '3 ' -(% ' ( 9 $( - -(% 9 $ %( 9 $( - -(% 9 $$(( &" ' ( % + ( - -(% % % .' ' ( % # % -(% # # %3 -(% # %3 $ # % -(% # # ; ' -(% #; !(( & -(% ( &" ' ( % $$(( -(% % % + '( % % ( $ ' ('( " %' % % $ ' %.( % , -(% , # , +(- ( -(% #, .( *& -(% .( : *& -(% : , -(% , xr68c681 1 read mode registers write mode registers address (hex) register name symbol register name symbol $ -(% " ' " $ -(% " ' " % -(% " ' '3 ' -(% " ' %3 $ # % -(% # $ -(% " ' 1 ! 9 $( - -(% " ' 9 ! 9 $( - -(% " ' 9 = # , - -(% #, !(( & -(% 6 # % -(% # # %3 -(% # / .( *& -(% .( *& -(% @ .( : *& -(% : .( : *& -(% : < $ -(% " ' * *" * $ -(% " ' * *" * % -(% " ' * * '3 ' -(% " ' * * 22;2 $ -(% " ' * * * ! 9 $( - -(% " ' * 9* ! 9 $( - -(% " ' * 9* # ; ' -(% #; # ; ' -(% #; # , #, , +(- ( -(% , ,@ , 2 .( $ , *(% $ ,* .( $ , *(% $ ,* table 1. duart port and register addressing note: the shaded blocks are not read/write registers but rather, ?address-triggered? commands. xr68c681 = table 1 ( $(' % ' ' (% c( $ ( h $ -(% %i %% '( $ ( ' + % h $ -(% i ( % (% h $ -(% i ( ( ' (.%&% 22 ' ( (% h ( ( - i ' -(% , % %++(! h i (% % $ $ + & + % -(% %& % ( $ + " - ('&" ( ' % * 9 " ' % + ( ( % (+ + $$ %% + -(% + -(% " ( $( & + ( - & $ ( '' %% -(% ( ( ' ( h ( i -(% ( $ % '' % ( h22 ,#82i ' $ % ( 3 $ h22 ,#82i ' $ ' (%% $ & (( - ( $ ( ' f% ' $ -(% + " $ -(% %" ( ( -( ' " % -(' $$ %% + % $ + '( % + ' $ & $ -(% % $(%'%% $ ( $ ( ( section g.3 b.2 command decoding 2' ' (% c( $ ( ' $ -(% # - " + % ' $ -(% % .$(% %( " .$(% ' ( " - ( +'((( - % ( % + (%' % ' $% ( + + ' ' $ -(% (% % $ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miscellaneous commands enable/disable transmitter enable/disable receiver ( - ! j 8 - j 2 ! j (% ! j 8 ;($ % j 8 - j 2 ! j (% ! j 8 ($ $ % table 2. command register - cra, crb + '( + ( + ' $ -(% % (% +( & % (- + $ (% ( (% % $ ( $(% %( $. ' ( ( + ' $ -(% (% % $ ( 3 % ( % + (%' % ' $% table 3 $ +( % ' $% %% '( $ ( ( + ' $ -(% % , % ( ' $% / - * / ++ '% & + ' + ' $ -(% f% ' 9 " ' $% / - / ++ '% %&% ' ( ( xr68c681 6 bit 7 bit 6 bit 5 bit 4 description null command: reset mrn pointer: % % ' f% ( ( reset receiver: % % ( $(($ ' ' ( % (+ $ % % ( $ ' ( (% $(% $ $ # (% +% $ reset transmitte 4 % % ( $(($ ' %( % (+ $ % $ ( $ 5 (% + ' $ (- reset error status: % ' ( $ * 3 *" , (& 2 ,2" ( - 2 2 $ 2 2 %% (%" m@41n '(+('&" (+ $ " + (' ' (% % h* '3i $ " (% ' $ ( % + ' ( ( $(' % ( %% -(% # '3 $ " ' ( ,2" 2" 2 * '' %" (% ( ' ( +-- $ ( ' %% -(% " ( (% ' $ (% (%% $ #+ 2 $ " + (' ' (% % h ' i 2 $ " ' % + % -(% + ,2" 2 $ * + ' $ ' ' & ' ' %(' # h ' i 2 $ " % + % ( $(' % (% % $ & ' ' (% + 9 2 ( $(' (% &% +-- $ % h* '3i 2 $ ( $(' " $ c( % (% ' $ % reset break change interrupt: % ' f% 3 ' - ( %% ( start break: ' % 5 %( % $ % 3 #+ %( (% &" % + 3 & $ & $ ( ( % #+ %( (% '( " 3 -( % %(%%( + % ' ' % ( 9 (% ' $" (g" 52, % + 3 ( -( stop break: 5 ( ( - (- ( ( ( ( % 5 ( ( (- + ( ( + ! ' ' " (+ &" (% %( $ set rx brg select extend bit: % ' f% h ' ( *0 ' 2! $ *(i hi - !j clear rx brg select extend bit: % ' f% h ' ( *0 ' 2! $ *(i - !j set tx brg select extend bit: % ' f% h %( *0 ' 2! $ *(i hi clear tx brg select extend bit: % ' f% h %( *0 ' 2! $ *(i hi set standby mode (channel a): a (% ' $ (% ( 3 $ ( ' ' $ -(% " (% $ + ' + %( %" ' ( %" .( $ $$(( '( '(% ' ( % $& $ , % (% ' $ ++ '% ( + ( ' ( 8 ( (% % $ & $ % & ( 3( - h2 #;2 2i ' $ set active mode (channel a): a (% ' $ (% ( 3 $ ( ' ' $ -(% " (% $ + % $& $ $ % % ( reserved reserved table 3. miscellaneous commands, upper nibble of all command registers, unless otherwise specified. xr68c681 / # $$(( ' $% (' ( - ' $ -(% %" % ++ % h $$ %% (-- $i ' $% % ' $% (% $ ( table 1 " , 8 20#2 2#80ik $ + ($ (+( $ & ( - h% $ $i ( '(+('&" % ' $% 4 82.#2 8 , 82.#2 8 2 , , *# 8 :2 , , *# 8 2' + % ' $% ( 3 $ & ( $( - (( - $ ( ' % $( - $$ %% % % % '(+( $ ( table 1 ! " 82.#2 8 (% ( 3 $ & ' $ + $( - $$ %% 2 / , % (% h $ ( i ( % ( '( - ' % + -(% $ % & ( - ( " ( % % (% ' $ k (% .( ( ( (( ' ( - $ ( $ $(%'%%( ( ( + .( %" % % section d.2 ! + h $$ %% (-- $i ' $% (% h2 , , *# i $ (% ' $ (% ( 3 $ & + ( - ( + $ $$ %% 2 / a % ( 3 % (% ' $ " .% (% % ( - ' ( (% hi ( ( , , -(% (%" ( ( , % '(+( $ % " ' - $ % + ( % ' % + ( $(($ (% ( ( , 9 ' " (+ ,mn (% % hi" % + ' % $( - ( " ," (% % -(' hi % c &" ' ( 3 + h2 , , *#i ' $ % h:2 , , ,#8i ' $ $ ( $ $(%'%%( ( ( + %" % % section f c. interrupt control block ( ' '3 % % & ( h# ( i ( ( '$ % # c % %(- #8 (% ($ $ (' & - $ %% $ '' ' + & + + ( - %4 %( 9 $ -(% * $& ' ( 9 $ -(% * $& ' ( # * 2 $ + ' ( $ * 3 ( % * 2 $ + .( ' $ - + ( ( %" #," #," #," #,1 ( ' '3 ' %(%% + # % -(% #" # %3 -(% #" %3 $ # % -(% # $ # ; ' -(% #; table 4 (%% % -(% %" $ ( $$ %% '( ( ( register description address location (in duart address space) # # % -(% 6 / $ & # # %3 -(% 6 / a ( & # %3 $ # % -(% / $ & #; # ; ' -(% / table 4. listing and brief description of interrupt control block registers $ % + ' + % -(% % $ +( $ % + %4 c.1 interrupt status registers (isr) ' % + # ( $(' % %% + ( ( ' $(( % #+ & (% ( ( % -(% % -- $ h (- i" ' % $( - ' $(( % (% '' ( - # - " ' % + # ( ( $(' ' %% " % ' % + ( c % + ( + + # -(% (% % $ % + % xr68c681 @ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter ready delta break a rxrdy/ ffulla txrdya j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % table 5. interrupt status register - (isr) bit format ( - ( $ ' + % (% (% $ +( $ isr[7]: input port change of state: #+ (% ( (% -(' hi" h' - + % i % $ ' $ #, #,1 ( % % $ % (' (% ( & $( - #, (+ #m@n j #m@n (% ' $ , % $ #, *& $( - #," % ( $ ( 4 ( $(($ # , ( ' - $ % +( % + ( $ ( %" + ( - - + $ ( $ $ %' (( + #," % % section e , % ( $ (% ( ' $(( " % % $ ( -%4 a ( ( $ ( + !(( & -(% " m14n # (% % " % (% % '(+&( - (' ( ( % % $ (-- h# , - i ( c % a ( -(' hi #m@n isr[6] delta break indicator - channel b: a (% ( (% % " ( ( $(' % ' * ' ( % $ ' $ -( ( - $ + ' ( $ 3 (% ( (% ' $ % , ( 3 % ' * h22 *2 7 9 802 #82 ,i ' $ ( + ( ( f% % % *2 7 ' $(( " % % section g.2 isr[5] rxrdyb/ffullb - channel b receiver ready or fifo full + '( + (% ( (% % ' $ & - ( - *m/n #+ - $ % ' ( $& ( $(' 5e*" ( ( $(' % % ' ' + $ (% ( 9* $ (% $& $ & , (% ( (% % ' ' (% %+ $ + ' ( $ % (+ -(% 9* $ (% ' $ , $% 9* #+ %( ' ' % ( 9* + $ ( " ( ( % -( + 9* (% h $i #+ (% ( (% - $ % # ( $(' ::*" ( (% % ' ' (% %+ $ + 9* $ %+ '% % 9* ' + (% ( (% ' $ , $% 9*k $ & h ( -i # " 3( - + ! ' ' #+ ' ' (% (( - ( '% 9* (% +" (% ( ( % -( + $ ( " ' ' (% $ $ ( 9* isr[4] txrdyb - channel b transmitter ready (% (" % " ( $(' % 9* (% & $ (% $& '' ' ' + , ( (% ' $ , ( % ' ' 9*k $ (% % -( " ' ' (% %+ $ 5e (% % %( (% ( ((& $ $ (% ' $ %( (% $(% $ ' % $ $ ( 9* ( %( (% $(% $ ( %( $ xr68c681 < isr[3] counter ready # #2 $ " . .( ( % #m1n ' ' '&' + % %c ( ,1 ( #m1n ( ' $ & ( 3( - h, 82i ' $ * ( ( $" ( #2 $ " h, 82i ' $ ( % . # 82 $ " (% ( (% % . ' % ( ' / $ (% ' $ . (% % $ & h, 82i ' $ a .( (% ( 82 $ " (% ' $ ( % ' isr[2]: delta break indicator - channel a %% ( + (% ( ( $(' % ' ' ( % $ ' $ -( ( - $ + ' ( $ * 3 * (% ( (% ' $ , ( 3 % ' h22 *2 7 9 802 #82 ,i ' $ ( + ( ( f% % % *2 7 ' $(( " % % section g.2 isr[1] rxrdya/ffulla - channel a receiver ready or fifo full + '( + (% ( (% % ' $ & - ( - m/n #+ - $ % ' ( $& ( $(' 5e " (% ( ( $(' % (% % ' ' + $ ( 9 " $ (% $& $ & , (% ( (% % ' ' (% %+ $ + 9 $ (% ' $ , $% h %i 9 #+ %( ' ' % ( 9 + $ ( " ( ( % -( + 9 (% h $i #+ (% ( (% - $ % # 9 + ( $(' :: " ( (% % ' ' (% %+ $ + 9 $ & %+ $ ' ' '% % 9 ' + # (% ' $ , $% 9 #+ ' ' (% (( - ( '% 9 (% +" (% ( ( % -( + $ ( " ' ' (% $ $ ( 9 isr[0]: channel a transmitter ready (% (" % " ( $(' % 9 (% & $ (% $& '' ' ' + , ( (% ' $ , ( % ' ' 9 k $ (% % -( " ' ' (% %+ $ 5e (% % %( (% ( ((& $ $ (% ' $ %( (% $(% $ ' % $ $ ( 9 ( %( (% $(% $ ( %( $ c.2 interrupt mask register (imr) ( %3 -(% (% ha ( &i -(% (' % % % ' ' $(( % ( '% (%% ( c % ' %% # $%" % % ( + %3( - '3( - ' ( ' $(( % + '%( - (%% ( c % + " ( + + # (% %% (& % % # 9 " + ' %%" ( + + # (% % $ ( + ( - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter ready delta break a rxrdy/ ffulla txrdya j++ j j++ j j++ j j++ j j++ j j++ j j++ j j++ j table 6. imr bit format xr68c681 #+ % (% % ' ( ( " .% % $ ( hi (" ( ( #" ' % $( - ( ' $(( :(3 (% " $(% %3 ' ( ' $(( '%( - ( " % % $ ( hi ( '( ' % $( - ' $(( ( % % $ ( hi% (% -(% , % # (% h ( &i -(% " $ + " ' $ & ' %% c.3 masked interrupt status register (misr) ' % + # -(% (% %('& %% + 8( - # $ # - # j m# %n m# %n ((( + ( ( % & $( - # (% (% ( ( # ' -- h (- i $ ( ' % $( - ' $(( % & $ & # + " % " + ( - $( - ( %% -(% " ( 3 (%( % + k $ ! ' h( & (i 8 + # $ # ' % ( ' # (% ha ( &i -(% $ ' $ & ' %% " ' % + # ( % $ (% %&% &" + ' $$(( $ $ % + $ c( $ % (% '((& ' (( $ ( % + # c.4 interrupt vector register, ivr /< +(& + (' ' %% % % % ' $ ( ' %%( - '(+('&" $ ( - ( % ('( -" ( % $ ( '3 $- %(- " + , " & '( - ' % + #; $ %" $ & , ( - ( " ' % + #; (% $ '( ( &" ( ( % (' ( + ( ( - %($ % + " ( ' $ ( ('( %" ' % + #; '' (% ( -%4 #$ (+& ( ' % c %( - ( , $ ( '( +k $ ' - ' '( " ( - &" ' ( % ( ( % (' ( + ( ( - % c &" $ ( - ( (((g( + " % ( $ #; ( !$ '( % + % = / /= - / 66 " ( '%( & (% (% - + %" ( /<!f% !' ( ' " % $ + h % # ; ' i & '( + h i ( % (' ( ' + $ & (&( - ' % + #; & = 9 ' " % % $ 3 ' 3 % ( % (' ( % % m % + #;n = ( - & 5/</<" (3 & /< % ( % ( $ (' % $ %(- $ %' $ + ' % + ( #; + ( - 22 ' $(( (% / % c &" (+" $ ( - h( '3 $- i '&' % ! % '( , $% / + k $ h ( (((g $ # ; ' i !' ( ( - $ c.5 limitations of the duart interrupt structure ( % ' ++ $ & % % - - ( % ( % % ' ( 9 $ 9 # ' $(( %k h .( $&i ' $(( " $ ' - % ( 3 ' $(( ' ( 9 " %($ + h * 3 $(( i" f% ( % ' $ % + ( c %% $ ' ( % %' % , (& 2 ,2" ' ( 2 2" ( - 2 2 % $ % ++ % ((& ' +(- + % & '' ' + & + % ' $(( % % (%" + " ' $ $ h($ i ' ( $ & + c & $( - %% -(% k $ ' '3( - + & g ( % (% (% % '(& '% (+ % % % $ h ' i m6n j c.6 servicing duart interrupts /< +(& + (' ' %% % % % ' $ ( ' %%( - # ' $ ( ' %%( -" ( $ (' " % %( + c %( - ( " ( ($ (+& (% + (' ' %% " $ ( - h# '3 $- i '&' ' (' ' %% 3 % (' ( $ (' (% c %( - ( " (' ' %% ( $ ( '( + ( ( % (' ( ( &" $ ' - ' '( $ - + %( - h; ' $ # i ' %%( - h, $ # i ' %%( - (% %(- (+(' ( xr68c681 ( ' ((' ('( % %( - & ( % $ (' % # h, $ # i ' %%( -" $ '( + ( c %" (' ' %% ( - - $ ' $ & ( $ (' ( $ $ ( $ (' '%( - ( & + (% ( - ' $ (% ' $ ' (' ' %% ' - ' ( ( % (' ( ( c( $ ' + % ( $ (' % $$% ( '& ( $ $ (' $ '' $ ( - ' $ ( ' %%( - figure 2 % % %( (% ( + ( +' /< ' %% + ( % (' ' %($ ( % # 2 ' $ , ( (& '( $ ' $ figure 2. simple illustration depicting the interfacing of the xr68c681 duart to a 68000 processor xr68c681 #8 # 7 @ 7 mc68000 processor #,: #,: #,: 7 @ xr68c681 figure 3 % % $ ( $ %' (' + 5/</< $ (' ( +'( - /< (' ' %% (% +(- % % & ( ' %%( - ( + (' ' %% . ( +' $$ %% $ ' $( - '( '( & + $$ %% % (% < 1 (% ( '$ $ (% '( '( ' %(%% + h# , ( (& 2 ' $ i 8@=:=<" $ 1 ( < ( $ ' $ % 8@=:1< $(%'%%( % %" + % 8@=:1< $ (' % $ h# 7 ' $ i $ (% $ h#. ( ' ' $ i # (% +(- " % ( ( (& + = + '( $ %' (( + (% '( '( + % #+ c( % % (' + , " ( ( %% '( " $ ( " %(- " #8 a (% %(- -- % h i ( ( (& ' $ 8@=:=< ( - ( ( ( (& $ % (% ( (& , # (% '% " ( ( (& (% = #,: j " #,: j " #,: j # % % ( (& = ( c %" , ( ' '3 ( %3 (% + (% ( %% -(% ( $ $ ( % ( ( (& #+ % ( ( (& (% = %%k , ( '3 $- $ -( % (' + (% ( c % #+ % ( ( (& (% 6 - " f% ( c % ( % (' $ ( ' ( + (- ( (& ( % ' (' ' %% $ '($ % % (' (% (' ( c %" ( ( $ % & %% ( - + '( $ % j " j " j " ( $ ( $(' (% ! % '&' ( ( '3 $- '&' $$(( &" /< , (% ( $" ( ( $$ %% (% " " $ 1 " ( ( (& " ( $$ %% (% = 1 % -(' + " , ( '3 $- (% ( c % & % ( - j" j" 1 j " $ = 1 j ' + '( $ % % " 8 8 - @=: ( %% + ( % + h# 7 ' $ i $$(( &" $$ %% ( % %% $ ( $ % ! % '&' ' ( (% %% $" ( + # 7 $ ' $ ( % %% $ a ( % %% $" # 7 $ ' $ ( %% $ h# 7= " & %% ( - # 7 ( + # ( # 7= %(- ( - %% $" $$ %% (%" < 1 " $ - $$ %% $ ' $ % 9 " (+ + % $$ %% (% -(' hi " h#. ( ' ' $ i ( % $ # (% +(- " $ ( %% $" & %% ( - ( + , % $ % c( (f% ( %% $ ( $ % $ h# '3 $- i '&' & c( % (% h# 7 i ( %% $ # % % %% ( + # 7 ( " ( ' ' % + #; # ; ' -(% $ % @" ( ' $ & , ' % ' $ ' % + #; $ %" ( ( %% 7 ( $ ( + , $ (% $& $ + $ % , ( ! ' (% h $i ( ($ (' ( & $ '&' ' (% h $i '&' (% ' $" , ( - & -( - # 7 ( + k $ (" ( " - 7 , ' 7 % - $" ( '&' (% ' $" $ ! % $ $ ( '&' % ( (3 & $ $(' $ % ('( - ( #+ % $ & ( (((g $ #;" ( % -( - /= = / $ 66 / " , ( (& (% & =" ( $ $ ( '( " ( &" + ( % (' ( + $% (% $$ %% '( ( $ $ ( - ' + , $ , ( ' - ' (% '( ( %&" % % % ( ( % (' ( !(%% '( ( %&% & #+ % % +( $ ( (((g #;" (% ' % ( & $ + / 5/</< $ (' " (3 & /< % ( % ( % $ %(- $ $ + + ( ( ' -(% % / #+" $ ( - ( '&' " , $% / + #;" , ( (& (% & =" $ ( ' - ' h ( (((g $ # ; ' i !' ( % (' ( " ' $ 1 / ( & a , % & % (' $ ( $ ' $(( % '%( - ( c %% + (( $" #8 + ( - $ xr68c681 @ /< ' $( - ( '( & $$ %% < 1 #)@ @ ;'' # 6 6 # 7 # 71 @ 6 ' $( - ( '( & = 1 1 #)1 #) #8 # 7 #)/ @ / 6 8@=:1< # 7 ' $ # 7@ # 7/ @ # 76 #. ( ' ' $ $$ %% 8@=:1< 1 = @ 1 6 #)6 8@=:=< #) = # 7= 1 7 #,: 1 .a 7 5/</< 1 = .a #,: #,: #)= @ / = 1 @=: / = 1 1 @ 6 = = figure 3. detailed schematics of the xr68c681 interfacing to the 68000 processor # 7 8 xr68c681 1 figure 4 % % (( - $(- $ ('( - % c ' + % ( '' ., ( +' " $ ( - ( % '&' 1 ;2 figure 4. xr68c681/68000 cpu interrupt cycle timing #8 7 # 7 @ #,: #,: = 1 interrupt service routine l '( % + ( % (' ( 4 )('3& ($ (+& ' $(( '%( - ( c % )('3& % (' ( & (( ( - ' $(( '%( - # # $ ($ (+& '% + ( " , % $ ( %% -(% %3 $ # % % -(% + ' % + # ($ (+( % ' $(( % '%( - ( c % section c.1 $ +( % ( + + # $ $(%'%% % ' ' + (% ( ( # d. timing control block (( - ' '3 % % % '(+& ( % .% (% % %( $ ' ( $ ' ' (( - ' '3 ' %(%% + + ( - %4 %'( ( '( *( 0 / ( .( = 2! # ,( % ' '3 %( % $ ' ( %" $( '& '3 ' -(% % 14 5% xr68c681 = . ( ! m= /n 5* #, figure 5. block diagram of duart timing control block , % -(% % " : 14 5 ! 14 5 ! 14 5 !* 14 5 !* #, 5* #,6 5* #,= #,1 ! (($ & / 5 m@n 5.:7 5 (($ & / *( 0 %'( ( '( ( figure 5 % % '3 $(- + (( - ' '3 + 5/</< $ (' 2' + (( - ' '3 (% $(%'%% $ ( + ( - % '( d.1 oscillator circuit: ' &% %'( (% &('& ' ' $ ! & ' %% 5.:7 $ 5 ( % %'( '( '( ( ( ' ( + '( % % $ + % ' &% %'( " $ ++ % %( - %'(( - %(- " + % & ( - " $ .( ' &% : %(- + c '& + 9g $ = 9g (% c( $ + ( + 9 " ' &% : %(- + c '& + 1/ ( + % $ $ ( % & ( - table 3 figure 6 % % ' $ $ %' (' + 5 : %'( '( '( & #+ % $ %( % % % + %( - ' &% %'( " figure 7 % % ' $ ' %% & '( '( & '' (% (% l '( xr68c681 6 figure 6. a recommended schematic for the xtal oscillator circuitry xr68c681 5 5 1/ &% note: the user also has an option to drive the oscillator circuit with a ttl input signal, in lieu of using a crystal oscillator. if this approach is used, the ttl must be driven into the x1/clk pin, and the x2 pin must be left floating. #+ % $ %( % % % + %( - ' &% %'( " figure 7 % % ' $ ' %% & '( '( & '' (% (% l '( 5 5 xr68c681 e @=9= 5 ( % + % 1/<=9g figure 7. a recommended schematic to drive multiple duarts from the same crystal oscillator xr68c681 / d.2 bit rate generator *0 *( 0 '' % (( - + %'( '( '( $ - ' '3 %(- + 1 ' & % $ $ ' ('( ( % -( - + 6 % 6 7% , % *0 ( & - % % $ $ ( % (+ %'( '( '( (% ( - 1/&" ' ' '3 + c '( % + *0 / ( % % % % ' % ' + $(++ % % + ( %" - $ + *0 (% % '( (% $ & % ( - ' ( - m@n (%( - + % % % + ( %" + *0" (% % $ ( $(%'%%( + '3 ' -(% % % ( section d.5 '3 $(- + *0 '( '( & (% % $ ( figure 8 5.:7 5 figure 8. block diagram of the bit rate generator portion of the timing control block %'( ( '( *( 0 ' % $ * m@n *m14n 14 5 !* *m@4=n 14 5 !* m@4=n 14 5 ! m14n 14 5 ! xr68c681 @ d.3 counter/timer (( - ' '3 % ' ( % / ( .( . . (% - / ( $ ' (' ' % + % (( - % ' % % (% ( figure 9 % % '3 $(- + '( '( & % $( - . % '( + % (( - % ' % + .( ' $ & (( - ( $ m/4=n !(( & -(% (% / - = , % % table 7 + ( % ( .( $ " $ (( - % ' ' % + (% m/4=n . (% ( ' '3 % ' -(% % + % % - ( - + %( % $ ' ( % (($ & / (($ & / .( figure 9. a block diagram of the circuitry associated with the counter/timer , % -(% % " : #, %'( ( '( 5 5* m= /n .de ,1 $ * 14 5% bit 6 bit 5 bit 4 c/t mode timing source 2! # #, 5 5 '3 + ' %( 5* 5 '3 + ' * %( 5.:7 # (($ $ & / ( 2! # #, ( 2! # #," (($ $ & / ( 5.:7 # ( 5.:7 # (($ $ & / table 7. acr[6:4] bit field definition - c/t xr68c681 < d.3.1 timer mode: , % + . $ %" ( $ (% & $ (' (% + '( + ( % '( 9 " + ' %%" ' $ (% % $(%'%% $ # ( $ " . '% % - $(($ $ - % %c % ( $ (% (' ( ' '3 ( $% + ' % + .( -(% %" $ : . ' % $ % - ( - ( $ $' /5 ' '3 + & ( ($ $ & *0 %c " (-( ( - + . (% ( " ,1 #+ . (% - $ ( ( $ " + c '& + %( - . %c ' ! %% $ % + %4 c/t output frequency = fsts m ctur n < + m ctlr n where: f sts = the frequency of the selected timing source (see table 7 ) [ctur] = the contents of the ctur register in decimal form [ctlr] = the contents of the ctlr register in decimal form ( ' . (% $ $ % /5 ' '3 %(- & '( '( &" %( - ( (% ./ + c '& + . %(- + " ( " $ ( $ + . ' ! %% $ % + %4 bit rate = fsts 1 m ctur n < + m ctlr n ' % + $ : -(% % & ' - $ & ( " ( & -( 3 ++ ' ! + '&' + %c . -( % ( %( - % ( .: ' ( + $$ %% (-- h 82i ' $ table 1 . % ' ( %& %% c h 82i ' $ '% % . ( ' (( - '&' $ -( (( - '&' %( - ' % % $ ( $ : 82 2 e %% (" ( # % -(% #m1n" (% % ' ' '&' + %c (% % % + . % ( $(' ( - " (+ ' $(( (% - $ - ( ( # %3 -(% # #1@ ' ' $ & (%%( - $$ %% (-- $ h, 82i ' $ table 1 # #2 $ " " ' $ $ % '& % . d.3.2 counter mode # ' $ " . ' % $ + % % ( ( .:" -( ( - ' ( + h 82i ' $ 82.2 e %% ( #m1n (% % ' ( - ' + / . ( ' ( ' % / $ $ + ( ! ' ( - / ( ( (% % $ & , ( h, 82i ' $ #+ ,1 (% - $ + ." ( ( (- ( ( ' (% ' $" (' ( - % # % (- % $ #m1n (% ' $ . (% % $ ( h, 82i ' $ h 82i ' $ ( ' (% ( - % % ' ( % ( .: , & ' - ' % + : & ( ' 3 % ++ ' & + %% c 82 ' $ #+ % - $ ( % % % $ $ % $ + ! '&' xr68c681 d.4 external inputs % + % + # , ( % #, #,6 % $ % $( ' ! ( % (( - ' '3 % (( - % ' % + %( % $ ' ( % + ' % , % % ' % '(+& ' '3 %(- " ( $ + % ! ( %" (% 5 /5 ' '3 %(- k ( ' '3 % ' -(% % % $ ( $ $(%'%%( ( ( % $ ( + '( " % % section e d.5 clock select registers, csra and csrb # figure 5 " '3 ' -(% % % 14 5f% ' '3 % ' -(% % % % ' % ' (' ' '3 %(- % ( $ ( %( % $ ' ( % + ' % % % % ' 1 $(++ % $ $ ( % + *0" .( " % ! ( % (( - % ' + %( % $ ' ( % table 8 $ table 9 % ( % ( ' % + % $ ' '3 % ' $ (( - %( % $ ' ( % bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ' ( '3 ' %( '3 ' table 9 table 8. bit format of the clock select registers, csra and csrb field bit rate csr[7:4] acr[7] = 0 (bit rate set #1) acr[7] = 1 (bit rate set #2) csr[3:0] x=0 x=1 x=0 x=1 6 @6 @6 6 1=6 1=6 1=6 1=6 6 6 1 1/ 1 1/ / ==7 / ==7 <<7 <<7 6 6@/7 6@/7 = 67 = 67 =< =< =< =< @ < < @ / / / / 1<=7 7 7 1<=7 ( ( ( ( 2! /5 2! /5 2! /5 2! /5 2! 5 2! 5 2! 5 2! 5 table 9. bit format of the clock select registers csr[3:0] and csr[7:4] xr68c681 1 , % table 6 '% + % % '(+& + ( - %4 m@n % %(- (+(' ( * + !( ( & -(% 5 2! $ ( m@n (% * + !(( & ' -(% " $ ' %(& - $ & (( - !!!!!!! !!!!!!! " ( $ % ' " % '( & ( note: the b suffix denotes a binary expression. x = don?t care value). 5 ' 2! $ ( 2' %( $ ' ( " ( ( % ! $ ( ' % ' $ & (( - ( $ ' f% ' $ -(% - (% ( + ( ' + $ ( table 1 table 10 % (g % % ' $%" $ ( ++ ' ! $ (% register contents resulting action $ -(% " < / ! *0 ' 2! $ *( 5 j $ -(% " / ! *0 ' 2! $ *( 5 j $ -(% *" * / ! *0 ' 2! $ *( 5 j $ -(% *" * * / ! *0 ' 2! $ *( 5 j table 10. command register control over the extend bit note: if the user programs either nibble of the clock select register (csrn[7:4] or csrn[3:0]) with values ranging from 0 16 to c 16 , then the user is using the brg as a source for timing. however, these standard bit rates (presented in table 9) apply only if the x1/clk pin is driven with a 3.6864 mhz signal. if a signal with a different frequency (fo) is applied to the x1/clk pin, then the duart channel is running at the following baud rate: actual baud rate = m table baud rate value n fo 1/&" % ( '% + % $ $ $ %" ' + c '& + ' '3 %(- ( / ( % % % 1x vs 16x clock signals % h5 '3i $ h/5 '3i ( $ - (% ! + " ( (% ( $(%'%% ( ( - $ %(- (+(' ' h/5 '3i % % ' ( $ % ( $ & +' + / a % h5 '3i & % % %(- % ' ( ( $ (%" % $ ' '& ' '$ - '' '& ( % ' ( $ ( % + /5 ' '3 ( ( + 5 ' '3 + ( - - % ( ' (+& % % ' ( ( + ' % (% ' '3 $ & ' (( - % ' + (( - ' '3 #+ (% ' ( (% '( $ (% ' (( - $ + % ( %( " %( (% % ' '3 $ & (% ' (( - % ' 9 ' " (% - ' '3 + c '& + ' ( (% !'& % % + %( (% (% ' ' (%(' + %& ' % % ( $ ' ('( - ' ( $ %( - $ ' ( $ %( $ !'& % $ " %++('( $(++ ' % ( + c '( % + ' '3 % ' % ' ' ( $ %( ' ' ( ( % ( ' (( - ' %%" % % $ ( + ( - $(%'%%( % % ( $ %(%%( %&% % $ (' $ ( figure 10 (% %&% ' %(%% + %( 5 " $ ' ' ( 5 xr68c681 1 t x receiver r x transmitter t x clock r x clock figure 10. example of a serial data transmission system : % + %% ' ( (% ' '3 $ & % ' (% %(- & +% + %( " $ ' ( (% & %( - % ( $ ' ( ( $ figure 11 % % %% + (% figure 11. receiver (1x) sampling, if the r x clock is slightly faster than the t x clock. figure 11 % % % ( % ( ' ( f% %( - ( $ ' % ( $ ( (% ' -( - # (% '% " ' ( (% %( - ' % ( $ (" ( $ ( ( ( ( $" ( ' %'' %%( $ ( (% (% 3 % ' ( $ (+ #+ (% ' '( + ' ( $ (+" ( & % ( %(%%( $ ' ( + (% % ( $" % $ (' $ ( figure 12. xr68c681 1 figure 12. illustration of an error due to receiver drift. actual data 0 1 0 10101 received data 0 10100 101 figure 12 % % ' ( %( - (- ( % ( - + $ ( ( # (% ( %( - " ( (% +(- " ' ( % $ # % $ $ ' ( $ (+ ' % (+ ' ' ( (% % %( ' '3 # - ( " + (% h ' ' $i %&% (% + '( + (( - $(++ ' % 5 $ 5 ' ' '3 %(- % 9 " ( $ ' ' + ' ( $ (+ $ ( ((g *2 $ ( - % ( $ %(%%( " & % ( 3 ' " & ' ( %( - + ( a (% + (% & $" ' ( " $ '( + (" ( -( %( - (% ( & % ( - +' &('&" + % % $& %" (% % +' (% / 5/</< $ (' % '' $ % /5 ' ( %( - + ( + " ( % $ (' %" ' ( $ '% '' ' + (" ( ' ( ( -( %( - (% ( & +' + / 9 " + % /5 ' '3 ( $% % % $" ' ( ( %% (% ( ( ( ( ($ ( + ( ( $" $ ( ' % %( - + (" $ + %% c $ (% ( " - $ + ' ' " ' ( ( % % ( $ % 5 $ &" ' ' ( % ' $ ( ( % ($ ( + (" ' ( (" + ( " -( %( - % ( $ ( ( $ ( % % figure 13 + ' ( % ' ( $ , (" ( ( ( '' ' + ( ' ( % $ ' $" (% %( - ' $ (% $ xr68c681 11 figure 13. the typical sampling pattern of each receiver within the xr68c681 device. @ /5 ' '3 ( $% % % ($ ( + *( *( , ( $ %( - ' (c ((- % & + % ( $ ( % & ( - $l% ' ( %( - ( " ($ ( + ( ( $%" ' ' ' ' %(% (% ' (% %'' %%+ + % %4 # ++ % ( $(' ' '( ' ( %( - ( # ((% ' ( $ (+ %( - ( $l% % &('& % (% < ( ' ' ? (& $ , (% + " (+ % % '% ' ( $ $ + / $k $ '( + (" ' ( ( -( %( - $ / ! / j 61"/ 9g 9 " ' ' ( % % $ @ 61/ 39g ' '3 % " ( ( 3 (% '( % ($ ( + ( (% ( " 61/ 39g ' '3 %(- (% $(($ $ & / - % ' '3 / 9g + ( ( - $ $ $ (% + ' ' 5/</< $ (' -( % % ( $ ' ! ( ' '3 %(- % ( 5 /5 ' '3 %(- a % (% -( ' (' % ( 5 /5 ' '3 %(- '3 ' -(% %" % (% $(% $ &% % /5 ' '3" ( $ ((- ++ '% + ' ( $ (+ % (% + $(% $ % 5 ' '3 + % + " %% ( ' ( - % ( $ % (% %& ' % ( ' ( 5 ' '3 d.7 application examples using the timing control block # $ ' (+& % + %% % ( ( (( - ' '3" ! % ( '$ $ example a: using the brg % % (% % ' ( $ %( $ + 63% ( ' % % $ + ( - % 1/$ 5 ( %k $ (( - 1/ ( 5.:7 ( ( 5 ( + ( - a ( / $ -(% (% % ( % %( *0 ' 2! $ ( 5 j 1 a ( < / $ -(% (% % ( % ' ( *0 ' 2! $ ( 5 j = a ( !!!!!!! (% % % '% h*( i p table 9 + (% $ % a %++(! $ % ( & ! %%( " $ ! $ % h$ f ' i + ( & ! %%( 6 a ( << / (% % % % ' ( $ %( ( + ' 63% table 8 $ table 9 xr68c681 1= example b: programming the bit rate via the counter/timer % % (% % %( $ ' ( $ /63% ( ' * , % (% (' ( (% ++ $ & *0 # (% '% % ' $ + ( - ( = 9g : %(- ( 5.:7 ( " ( 5 ( (% + + ( - a ( / $ / : (% % % %% ( . - ( - %c + + c '& j = 9g. mn j 9g 1 a ( m/4=n (% ( % . ( ( $ " $ % ' (( - % ' + . 5.:7 ( = a ( / * (% ( % '(+& (( - % ' + ' ( $ %( + ' * ( $ ( $ + . , % (% - $ ( (% ' +(- ( " . % % /5 % + %( $ $ ' ( $ $ + " ' ( '( '( & ( $(($ 9g %c & /" l% (3 + ' '3 %(- % (-( ( - + *0 %4 *( j 9g./ j /63% example c: using the external input ports % " ( $$(( ( - ' * /63% % 2! *" .% % %( $ ' ( $ % ( ' % $% + + % % % $ ( 2! *" - ( + ( -4 a ( !!!!!! , , +(- ( -(% (% % % 9g %c + . ,1 2! & ' ' ,1 ( #,1 $ #,= ( % & &( - 9g %c ( % ( ( % 1 a ( / (% % ( % '(+& (( - % ' + %( $ ' ( + ' ( $ ( $ + ( ( % #,1 $ #,=" % '( & $$(( &" (% % $ % % ( %(- 5 %(- % 9 ' " (% $((%( & / + (% %(- + " ( + ' (% % , % (+ % & (% ! " .% $ % %( + % ( - ( ' ( - % ( $ % (% %& ' % ( 9g 5 ' '3 %(- k ( $ ( ((g ( % xr68c681 16 d.8 explanation of clock timing signals % + (% % '( (% !( % '(+('( (( - * '3 % # %" (% %l ' % % ' + ' %($ ' +%( & % % % limits symbol parameter min. typ. max. units :7 5.:7 2! 9(- : ( % + :7 5.:7 &% 2! c '& 1/ .( 2! '3 9(- : ( #, # % + .( 2! '3 c '& #, # = 9g 5 5 $ 5 2! 9(- : ( ( #," #,1" #,= $ #,6 % + 5 5 $ 5 2! c '& ( #," #,1" #,=" $ #,6 + 5 /5 /5 9g + 5 5 5 9g table 11. the xr68c681 data sheet presents the following parameter specifications, in the ?ac electrical characteristics? t clk - x1/clk (external) high or low time &% $& (' -(' - ' + (% '( '( & + " '3" ''" $ + ' ((% $ $ ( $ % $ (' ( + '( & (% ' % (( + ( %(- ( $ 5.:7 ( % %($ (- $ % % f clk - x1/clk crystal high or low time (% % '(+( % - + + c '( % (%%( 5.:7 ( " ( ( ' &% %'( ( $ : ( %(- + " % ' & & $ = 9g (% ( t ctc - counter/timer external clock high or low time - ip2 input (% ' % (( + ( %(- " ( - ( $ #, ( + % & .( " ' %($ (- $ % % , % (% (( % ( % ( ( 5 " (' (% % ' %% '( $ ( #, ( f ctc - counter/timer external clock frequency - ip2 input (% ' % (( ( + c '& ( - ( $ #, ( " + % & .( % ' %('& % % %(- ( + c '& = 9g ' ( $ #, ( " $ %( & $ $ & .( (% % ' (% $ 5 " (' % % '(+( % ((% %(- % ( $ #, ( ( %" + % ! ' '3 % ' + %( $ ' ( % t rtx - rxc and txc (external) high or low time - via ip2, ip3, ip4 and ip5 (% % ' ' % (( + ( %(- " ( - ( $ - % ( ( %" #, #,6" + % % %( $ ' ( ' '3 % ' " ' %($ (- % (% % ' % ( % ( " - ( (% % ( % ( ( #, xr68c681 1/ f rtx - rxc and txc (external) frequency - via ip2, ip3, ip4, and ip5 (% % ' ' % ((% 5 $ /5 ! %(- % % $ ' '3 %( % $ ' ( % #+ % (% % % 5 ' '3" .% ' & & %(- ( + c '( % 9g (% ( ( %% ( ( + % % 2! #+ % (% % % /5 ' '3" .% ' & & %(- ( + c '( % 9g ( ' (% 9g ' '3 %(- (% /5 %(- " (% ( % ( !( ( + 63% # % &" (( - ' '3 -( % % ((& - ( & & $ % $ %( % (( - ' '3 -( % % '' %% + ( - % ' %4 1 $(++ % $ $ ( % ( *0 .( " (' ' ' +(- $ - ( % (' ( + *0 # % (( - * '3 ( % ( ( % (' % % + ! ' '3 %(- % - '% ( e. input port ( ' % $ % - % ( ' - $ % % + % ( % + % '( + '( % ' % + ( % (% ' $ ' $ & , & $( - #, -(% + % % + #, #,6 (- ( %(- #,m n ( %% ( -(' hi ( #,m n ( %(( " ( ( #, -(% :(3 (% " h i ( %(- #, ( %% ( -(' hi ( #,m n ( %(( " ( ( #, -(% e.1 alternate functions for the input port table 12 $ %' ( % % % + # , ( %" %' % ' '3 ( % $ $ + ' %(- %" $ ( '$ % ( + % & - + '( $ + #, -(% % ( % -(' % ( " - $ %% + (% - $ + '( xr68c681 1@ input port alternate function(s) approach to program alternate functions #, 4 $ ( + ' 8 4 (% ( (% '( : " + + '( #, ' - $ + '( % ( & % ( - m=n j $ ( $ $(%'%%( (% + '( " % % section g.3 #, * 4 $ ( + ' * 8 4 (% ( (% '( : + + '( #, ' - $ + '( % * ( & % ( - *m=n j $ ( $ $(%'%%( (% + '( " % % section g.3 #, d254 .( 2! '3 # 5*4 2! '3 ( + ' ( ' * #, ' - $ + '( % ! ' '3 ( + .( & % ( - m/4=n j m" " n $ ( $ $(%'%%( ( ++ ' + (% '( % % section d.2 #, ' % - $ + '( % ! ' '3 ( + ' ( + ' * & % ( - *m@4=n j m" " " n + /5 '3" *m@4=n j m" " " n + 5 '3 #,1 5 4 2! '3 ( + %( ' #,1 ' - $ + '( % ! ' '3 ( + %( + ' & % ( - m14n j m" " " n + /5 '3" m14n j m" " " n + 5 '3 #,= 5 4 2! '3 ( + ' ( ' #,= ' - $ + '( % ! ' '3 ( + ' ( + ' & % ( - m@4=n j m" " " n + /5 '3" m@4=n j m" " " n + 5 '3 #,6 5*4 2! '3 ( + %( ' * #,6 ' - $ + '( % ! ' '3 ( + %( + ' * & % ( - *m14n j m" " " n + /5 '3" *m14n j m" " " n + 5 '3 table 12. listing of alternate function for the input port pins e.2 input port configuration registers (ipcr) # , +(- ( -(% (% h $ &i -(% % % + ( - + '( %4 % 3 (' + + ( ( % 4 #, #,1" % ' - $ -(' % " %( ' % $ + (% -(% % 3 ' -(' % + % + ( ( % % c &" # , +(- ( -(% (% + '( & $(($ ( % '( %4 *(% @ =4 h - ( : -(' i #$ (+('( (% *(% 1 4 ' % + # ,( % #, #,1 ( + + # , +(- ( -(% (% % $ ( table 13. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 #,1 #, #, #, #,1 #, #, #, j8 je % j8 je % j8 je % j8 je % j : j 9(- j : j 9(- j : j 9(- j : j 9(- table 13. bit format of the input port configuration register (ipcr) ( + $(%'%%( + ' ( +( $" ( ( (% -(% + % xr68c681 1< bits 7 - 4: ?change in logic state? identification bits % ( +( $% h % $i $ ' $ & h - + ' %i % h - + ' %i ($ $ + ( ( % #, - #,1 #+ % h - + ' %i $ ' ' - ( -(' % ( & + % + ( ( %" & ( ($ (+& h --( -i ( & % ( - ' % $( - h i ( +( $ ( ( #, hi #+ h - + ' %i $ $ ' ' - + % " (' ( " & ( + ' (% & 3 ( - ' % $( - ( +( $% % hi # $%" (+ ( ( #,1 ! ( ' % ' - ( -(' % " ( @ ( ' ( -(' hi bits 3 - 0: ?the current state of input pins ip0 - ip3? % ( +( $% h $ &i $ + ' ' -(' % #, - #,1 ( ( % # $ h# , - + i ( " % $ + ( - a ( ( $ ( + ( + % + (% % $ , % (' (%" ( ( -(% " % $ $ ( + #, ( ( $(' (' + + ( % ( % ! ( ' $ ' - + % ( + #, % % % % + % ( % + " $( - #," ( % % h - + i ( " , ( $ ( 4 ( ( % -- $ +( % + ' -( - ( ( ( - # m@n bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 brg set select counter/timer mode and source delta ip3 interrupt delta ip2 interrupt delta ip1 interrupt delta ip0 interrupt j j table 7 j j 8 j j 8 j j 8 j j 8 table 14. acr- auxiliary control register note: this ?two-tiered? interrupt enabling/disabling approach, for the ?input change of state? interrupt allows tremendous flexibility for the user. setting or clearing the bits in acr[3:0] allows the user to specify exactly which input port pins to be enabled (or disabled) for generating the ?input port change of state? interrupt. setting or clearing imr[7] allows the user to ?globally? enable or disable this interrupt. xr68c681 1 f. output port ' %(%% + < ( ' % $ % - % ' % $ + (( - $ %% %(- % & ( & - ( - + $ -(% % " * $ " * $ % ' +(- ( -(% " , a % $ %% %(- % ( % $ ( " (' % ( % ( ( ( %' , - ( - (% ( $(++ + ' ( ( % &(' $ % '( '( & ' %(%% + , -(% ," $ ( % % % ' % + , ' % + ' % + ( % ! " (+ ( ,m6n (% % -(' hi" (% ( % ( ,6 ( ( - -(' hi :(3 (% " (+ ( ,m6n (% % -(' hi" (% %% ( ,6 ( ( - -(' hi ( - 3 % - ( - ( $$ (% ' $ % % '' (% (% + a (( - (% " % ( 3 + $$ %% (-- $ ' $%4 h2 , , *#i $ h:2 , , *#i # (% ( ( 3( - h2 , , *#i ' $" % (% % ( - (% -(' hi ( , 9 " (% '( %% ( % ( - ' % $( - ( %" -(' hik $ ' & ( % ( % + ( % $ (% ( , :(3 (% " h:2 , , *#i ' $ (% ( 3 $" % '(+( $ (%" ( ( , h' $i -(' hi 9 " ' % $( - ( % % -(' hi % % + ' ( ( ( ," + ( - , % ," (% hi + " % + ' ( " + ( - , (% -(' hi (% + , ' % $ ' $ ( $(($& ( (% % & $$ %% (-- $ h2 , , *#i ' $ % table 1 ( '' &( - $" $ %" % '(+&( - (%" ( ( ," % j % " j ' - ( (% ' $ & $$ %% (-- $ h:2 , , *#i ' $ % table 1 ( '' &( - $" $ %" % '(+&( - (% % j ' $" j ' - f.1 writing data to the opr/output port pins % ( $ ( " % + , $ ' % c &" ( % (% ' $ & h $$ %% (-- $i ' $% , *(% $ , *(% $ ' $ $ ++ ' + %( - % ' $% $(%'%% $ ( + ( - % '( f.1.1 set output port bits command ' ' $ % $ ( 3 h2 , , *#i ' $ (% % % (( - ' % $ % @ $$ %% 2 / + ,@ , & hi !(%% ( ( ' $ ' % + $ %" ' % $( - (" ( ( , (% % -(' h (- i & hi (% % $ % $ (% ( $$ %% 2 / " % + ' % $( - (" ( ( , (% ' - $ a ' $ % (% & %4 & hi (% % $ %" $ ( - % + h2 , , *#i ' $" ' % $( - ( (% % -(' h i $ + & hi (% % $ %" $ ( - (% ' $" % + ' % $( - ( (% ' - $ ! 4 % ' + , ,m@4n j m" " " " " " " n 9 ' " % + ( % % + %4 m,@" ,/" ,6" ,=" ,1" ," ," ,n j m" " " " " " " n #+ ( + ( - $$ %% 2 / k m@""n j m" " " " " " " nk %( - % + -(% (% + %4 ,m@4n j m" " " " " " " n % c &" % + ( % % + %4 m,@" ,/" ,6" ,=" ,1" ," ," ,n j m" " " " " " " n (% ! + h2 , , *#i ' $ (% (% $ ( figure 14. xr68c681 = state of output port pins (op7 - op0) # (( ,m@4n ( ,m@4n *%" @ $$ %% 2 figure 14. illustration of the ?set output port bit? command and its effect on the output port register and the state of the output port pins. # % &" + h2 , , *#i ' $k j k %% ( ' - + ,m n" ( , j k %% ( ,m n j hi" $ ( " , j hi f.1.2 clear output port bits command ' $ + ( 3( - (% ' $ (% & %(( + h2 , , *# 8ik !' % ( % $$ %% / + m,@"",n & hi (% h ( i (% $$ %%" ' % $( - ( ( , -(% (% % -(' h i $ ' % $( - ( " , (% % -(' h (- i & hi (% ( (% $$ %%" % + ' % $( - , -(% (" $ ( % + ( (% ' - $ ! 4 % ' % + , -(% " , j m" " " " " " " n % c &" % + ( % 4 m,@" ,/" ,6" ,=" ,1" ," ," ,n j m" " " " " " " n #+ ( m@""n j m" " " " " " " n $$ %% / " %( - ' % + -(% ( 4 ,m@4n j m" " " " " " " n " %( - % + ( % ( 4 m,@" ,/" ,6" ,=" ,1" ," ," ,n j m" " " " " " " n (% ! + h2 , , *# 8i ' $ (% (% $ ( figure 15. xr68c681 = state of output port pins (op7 - op0) # (( ,m@4n ( ,m@4n *%" @ $$ %% figure 15. illustration of the ?clear output port bit? command and its effect on the output port register and the state of the output port pins. m,@" ,/" ,6" ,=" ,1" ," ," ,n j m" " " " " " " n # % &" + h:2 , , *#i ' $k j " %% ( ' - + ,m n $ ' - ( % + ( " , j " %% ( ,m n j " $ % % ' % $( - ( -(' hi f.2 output port configuration register (opcr) ( % ' % $ % - % ( %" & ' ' +(- $ % $ ( + '( % table 15 (%% + '( % + ' + ( % xr68c681 = output port alternate function(s) , rtsa : c % $ + ' 8 4 (% (% '( : + + ' ( , rtsb : c % $ + ' * 8 4 (% (% '( : + + ' ( , txca_16x output: /5 %( '3 4 txca_1x output: 5 %( '3 rxca_1x: output: 5 ' ( '3 ,1 txcb_1x output: * 5 %( '3 4 rxcb_1x output: * 5 ' ( '3 c/t_1_rdy: .( $& + . p note: this output is an open-drain output when used as the counter/timer ready output. ,= rxrdy/ffull_a output: ' ( $&. # # $(' 8 4 (% (% ( + 5e. ::d + '( ,6 rxrdy/ffull_b output: * ' ( $&. # # $(' 8 4 (% (% ( + 5e. ::d* + '( ,/ txrdy_a output: %( $& # $(' (% (% ( + 5ed + '( ,@ txrdy_b output: * %( $& # $(' (% (% ( + 5ed* + '( table 15. listing of the alternate functions for the output port & + '( % + ( % ( % % ' $ & (( - ( $ , ( + + (% -(% + % bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op7 op6 op5 op4 op3 op2 j ,m@n j 5e* j ,m/n j 5e j ,m6n j 5e. ::* j ,m=n j 5e. :: j ,m1n j . p j 5*5 j 5* 5 j ,mn j 5 /5 j 5 5 j 5 5 table 16. output port configuration register - opcr note: opcr only addresses the alternate functions for output port pins, op7 - op2. op0 and op1 assume their rts roles if either mr1n[7] = 1 or mr2n[5] = 1. setting those mode register bits enables the rts function. otherwise, these two ports will only be general purpose output ports. g. serial channels a and b 2' % ( ' + ' (% % + $ ! %& ' % ' ( $ %( ' % ' ( $ $ & % ' ( ( - + c '& + *0" ." ! ' '3 % % ( - $ * %($ % $ ( (' ' ( $ %( + ' ' ( $ $ &" ' ' +(- $ ( ( % ( - $ %" (' % + + ' $ $(- %('%" % % ( 3 $ % $ + ( $ ('( % xr68c681 =1 # (% % '( ' ( %& % ( % $ $ ' ( % '% + %( $ ' ( $ +( (( + % + % %& % + % 5 %( ( + 5 %( '3 (- + 5 ' ( ( # + 5 ' ( '3 (- + (% % '( + $ % $(%'%% % % ' % ( ' ' % % ' % (% $ 4 %( %( 9 $( - -(% $ %( (+ -(% ' ( ' ( 9 $( - -(% $ ' ( (+ -(% % -(% $ -(% $ -(% section b.2 " $ ' $( - '3 ' -(% section d " (( - * '3 g.1 transmitter (tsr and thr) %( '' % $ + , $ ' % ( % ( ( % ( (% 5 ( " $$( - % " % $ ( (& (% % c( $ & %& ' % ' 2' %( ' %(%% + %( (+ -(% $ %( 9 $( - -(% 9 9 (% '& & # figure 16 % % %((+( $ (% ( + $ 9 , ( (( % %(%%( + % ( $ & (( - ' ' $ 9 ' ' ( $ $ ( $ ' %% $ - # " ( ( ' % ( - %(( + 9 " ' ' $ (% % ((g $ $ (% %( $ + ' ( ( 5 ( $ % , + , figure 16. a simplified drawing depicting the transmit shift regis- ter and the transmit holding register. 5 - ( - ( %( 9 $( - -(% 5 %( (+ -(% %( '3 + (( - * '3 xr68c681 == a %( (% ($ ( '( " 5 + (' ' ( ' ( %& 3( - -(' h (- i 9 " l% ( %(%%( + ' ' " %( % ' ( & - ( - ( ( (% %('& 5 --( - h i + ( ( $" + ( - ($ ( $ , ( + ' $( - ' ' # $( & + %(%%( + (" % %(- (+(' ( + ' ' ( % +( % + $ & - %%( & %(- (+(' (% #+ ' ('( ' '% + (" %( ( % $ h (&i ( % %(- (+(' ( + ' ' $ , ( figure 17 % % + + + %( 5 # (% '% " %( (% % $( - 6* / " ( < 8 ' < (% ' ' " 8 (&" *( figure 17. the output waveform of the transmitter while sending 5d 16 (8-n-1 protocol). *( *( %( #$ *( 5 ' - $ - ( c % , & % ( - #mn $ #m=n + ' % " $ *" % '( & # (% '% " $ - ( c % &( %( 9 $ & + ' ' % , ' % (' (% ( c % & (( - ' ' & 9 %( ' $ $(% $ ( ' $ -(% % table 2 ( section b.2 #+ ' $ (% (%% $ $(% %( " ( %( ' ' % ( 9 $ " %( ( ' ( %(( - + ( ( - $ ( ( 9 $ " ( & ' & & + ' ' % 8 ' ' % ' ( 9 ' # *:2 8#2 ' $ % (%% $ g.2 receiver (rsr and rhr) + '( + % ( ' ( (% ' ( % ( $ 5 ( k ' ( $" ( ' $ & , ' ( (% % % %( + ' ( - $ ' '3( - (&" (+ (& (% ( - % $ ' ( ' %(%% + ' ( (+ -(% $ ' ( 9 $( - -(% 9 9 (%" ( %% ' " & # ' ( ' ( % $ 5 ( " ( (% ' %% $ - + $%" $ (% ' $ + " $ (% %+ $ 9 (% ' ' (% ' %% $ - 1 & % + # ' ' ( $ ' ' ' % + # " ( ' h $i $ & , k ( $% 9 figure 18 $ ('% %((+( $ $ ( - + ' ( xr68c681 =6 # ' ( - ( figure 18. a simplified drawing of the receiver shift register and receiver holding register ' ( (+ -(% 5 ' ( 9 $( - -(% 5 ' ( '3 + (( - * '3 $ % $ & , ' ( + '( % & % %( - - 5 ( a + $ %( (% ($ " (% 5 $ ' % c &" 5 ( (% ' ( %& h 3( -i ( - (% ( $ ' ( (% ( '( $ (% ' (( - ' %%( - & $ 9 " + $ %( % $% (" ( (% 5 --( - h i" ' ( ' '3" (' (% / ( % $ ( /! ' '3" ( % %( - (% ( #+ ' ( $ ( % (% 5 ( (% %( h i + (% @ % " ' ( $ ' %($ % (% %(- ($ ( #+ 5 ( (% i i @ % " ' ( ( (- (% $ $ % % h (% i (% @ % " ' ( ( % ' %'' %%( ( ( ( $ ( % .$ ( ! ' '3 % + (% /! ' '3 (% + $ (+& $ ' $ h i ( 5 ( (% ( $ $ ( %(% % ( % ( ! ( %( - ' '3" $ ( ' ( - % ( $ % ($ (% % ' $ ( ( ($$ + (% ( ( $ , % (+ /5 ' '3 (% % ' $ + ' ( " %( - ' $ '' % ( ' $ & % ( ' ( ( ' ( % $ ' ( ' ( + ' ' + % (" ( ( ( % ' ( + ' ' f% * ' ( ( ' '3 (& (+ - $ ( % + , ( #+ ' ( % % 3 ' $(( (% ( $ (& ' '3 (+ & % ($k %'' %%+ ' ( + ' ' (% % $k $ ' ( ( % % $ % '' ' + ( + ! ' ' xr68c681 =/ receiver errors #+ ' ( $ % % h 3i" % $ ( + , (" ( - 2 2 (% +-- $ & % ( -" m/n j #+" ' ' ( + ' ' " %% c (& ' '3 (% ( ' '" , (& 2 ,2 (% +-- $ & % ( - m6n j #+ 9 % +" $ ' ' !(% $ ( k $ (+ $ % ( ' % $( - 5 ( k ' ' ( ( ( " $ h ' ( 2 i 2 ' $(( ( +-- $ ( % -(% m=n j (% ( %& %% ( %% + $ ( & (+ 5 ( (% $ %' ' $(( + ( ' ' ( $" $ , ( % $ ' $ , ( %( - % $ ( %' k ' ( $ * 3 ' $(( * (% % $ a (% ' $(( (% $ ' $ % ( -% h ' ( $ * 3i ' $(( (% +-- $ ( % -(% m@n j h* 3i ' ' (% $ $ ( 9 9 " + $ (% ' ( $ $ $ ( 9 ( 5 ( % h 3i ' $(( 1 ' % $( - h * 3i ( (% c % $ (+ - $ $ +-- $ ( ( %% -(% ' 5 ( % h 3i ' $(( " %% c ' ' % ( $ $ ( 9" $ ' % $( - h * 3i ( ' $(( ( ' -( c % $ (+ - $ $ +-- $ ( ( %% -(% ' - $ - ( c % , (+ 5e ' ( $& :: # ' $(( !(%% + ( ' 5e ' $(( !(%% % ' ' + $ !(%% ( ( 9" $ (% ( & (( - h $i $ $ & , :: ' $(( !(%% 9 (% ' & + $ ' '' & ' ' % + ( , % $ h $i # % ' % ' ( c % '' $ ( 5e :: ' $(( ( ' $ -(% % % ( % $ & % ( - #mn $ #m6n + ' % $ *" % '( & 2' ' (% c( $ ( % -(% % % $ ($ ' $ ( ( - + % ' % + % -(% % $(%'%% $ ( ( % '( % + $ % 9 " $ ( $ $(%'%%( + ( $ + % -(% % % $ ( + ( - % '( g.3 mode registers, mr1n and mr2n $ -(% %" % % '(+& ' % .% $ (3 ' % -(% % % % ' +(- ' % -- ( $ $% 3( - ' (c % (% ( ( ' + % -(% % $(%'%% $ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx rts control rx interrupt select error mode select parity mode select parity type number of bits per character j8 je % j!e j :: j ' j * '3 j a( , (& j ' , (& j 8 , (& j ( $ j 2 j $$ j 6 j / j @ j < table 17. the bit format for mode registers mr1a and mr1b xr68c681 =@ + ' ' (% '' %% $ ' f% ( ( % ( (% % & $ 22 & h22 ,#82i ' $ ( 3 $ ( ' f% ' $ -(% + & $ ( " ( ( ('& ( bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 channel mode tx rts control cts enable tx bit length j 8 j 2' j : ' : j : j8 je % j8 je % j 6/1 j /6 j /<< 1 j @6 = j <1 6 j <@6 / j 1< @ j < j 6/1 j /6 j /<< * j @6 j <1 j <@6 2 j 1< j table 18. the bit format for mode registers mr2a and mr2b mr1n[7] - receiver request to send control $( (&" c % $ (% %% $ - $ & ( 3( - h2 , , *# 8i h:2 , , *# 8i ( ( 9 " (+ m@n j (% % " ' ( ( ' -( + '(+('&" % ( - (% ( ( ' ( - (+ (% 9 (% + (% h+ ' i ' (c (% % + ( ( - ' ( % figure 24 % % $(- (' (% % ' ( ' $ c % % $ ' +(- ( $ + '( mr1n[6] - receiver interrupt select (% ( % '% ( 5e %% ( :: %% ( + ' % $ % ' ( ( + - ( - ( c % , " #mn + ' $ #m6n + ' * mr1n[5] - error mode select (% ( ' % ( + # %% (% ,2" 2" ' ( $ * 3 + #+ (% ( (% % hi" (% (' ' ( ( h ' i $ #+ (% (% (% % hi" (% (' ' ( ( h* '3i $ # ' ' $ % %% (% & & ' ' (% ' & + # # '3 $ " % (% % '( -(' + %% + ' ' % ' ( - + # %( ' % h22 2 i ' $ + ' % (%% $ mr1n[4:3] - parity mode select #+ ha#9 , #ei h 2 , #ei ( (% - $" (& ( (% $$ $ %( $ ' ' % $ ' ( + % (& ' '3 ' ( $ ' ' % section h.2 + $ %' (( + ( $ ( xr68c681 =< mr1n[2] - parity type select (% ( % '% 2;28 (& (+ ha#9 , #e 2i (% - $ $ % + + ' $ (& ( (+ h 2 , #ei $ (% - $ # ( $ $ ( % '% % + . +- ( (% ( % ++ ' (+ h8 , #ei (% % ' $ ( m=41n mr1n[1:0] - bits per character select '% + (% %( $ $ ' ( $ ( $ +( $ + ' ' (% $ % ( '$ " , #e" $ , (% mode register 2 (channels a and b) + ' ' (% '' %% $ ' f% , ( ( % " (' '' % + & '' %% ' f% -(% % c $% ( % $ % ' - ' % + ( mr2n[7:6] - channel mode select 2' ' ( + + $ % ( - m@4/n j ' +(- % ' ( $ # (% $ " ' ( $ %( ( $ $ & figure 19 % % $(- $ ('( - $ ( ( ' ( (+ -(% # ' ( - figure 19. a block diagram depicting normal mode operation 5 ' ( 9 $( - -(% 5 $ % $ & , %( (+ -(% %( 9 $( - -(% 5 5 - ( - ( < < $ % , $ + , xr68c681 = ( - m@4/n j ' % ' ( (' ' $ " (' ('& % (% ' ( $ $ figure 20 % % $( - $ ('( - (' ' $ ( + ( - ' $(( % & ( ( (% $ ' ( $ $ (% %( $ ' f% 5 ' ( % $ %( $ $ ' ( 9 $( - -(% # ' ( - ( figure 20. a block diagram depicting ?automatic echo mode? operation 5 5 ' ( (+ -(% $ % $ & , %( (+ -(% %( 9 $( - -(% 5 5 - ( - ( < , % '' %% %( 1 ' f% 5e $ 52 %% (% ( '( = ' ( $ (& (% ' '3 $ (% - $ + %(%%( %" %( $ (& (% % ' ( $ 6 ' + ( - (% ' '3 $ % (% %( $ % ' ( $ / ' ( $ 3 (% ' $ % ' ( $ ( ! ($ % ( (% $ ' $ @ , ' ( ' ('( % % &" , %( ( 3 (% $(% $ 2' ' ' ' +(- $ ( + $(- %(' $ % local loopback mode (% $ (% % ' $ & % ( - m@4/n j figure 21 (% $(- $ ('( - ' '3 $ ( xr68c681 6 figure 21. a block diagram depicting ?local loopback mode? operation 5 ' ( 9 $( - -(% ' ( (+ -(% $ % $ & , %( (+ -(% %( 9 $( - -(% 5 $ % , + , < 5 ; < # (% $ 4 %( (% ( & ' ' $ ' ( ( %( ' '3 (% % $ + ' ( 1 ' f% 5 (% $ 3( - (- = ' f% 5 ( (% (- $ 6 %( (% $" ' ( $ $ $ / , %( $ ' ( ' ('( % ' ( & xr68c681 6 remote loopback mode (% $ (% % ' $ & % ( - m@4/n j figure 22 % % $(- $ ('( - '3 $ ( # ' ( - ( ' ( (+ -(% figure 22. a block diagram depicting ?remote loopback mode? operation 5 ' ( 9 $( - -(% %( (+ -(% %( 9 $( - -(% 5 5 - ( - ( 5 note: the cpu has no access to the serial data during remote loopback mode. # (% $ 4 ' ( $ $ (% %( $ ' f% 5 ' ( $ $ (% % , $ %% ' $(( % ' '3 $ 1 , (& $ + ( - % (% %( $ % ' ( $ = ' ( % $ 6 ' ( $ 3 (% ' $ % ' ( $ ( ! ($ % ( (% $ ' $ mr2n[5] - transmitter request-to-send control $( (&" c % $ (% %% $ - $ & ( 3( - h2 , , *# 8i h:2 , , *# 8i ( ( & %&% % + 9 " % ( - m6n j % ' %( - ('&" ( ( + ' ' % ( $ 9 %( $ $ & figure 26 % % $(- (% %( ' $ c % % $ ' +(- ( $ + '( mr2n[4] - clear to send control #+ (% ( (% " ' % ( #, + ' " #, + ' * % ++ ' %( #+ ( (% hi" %( ( ' '3 % + (% ( ' ( (% ( $& % $ ' ' #+ (% h i" ' ' (% %( $ #+ (% (- - $" 5 ( % ( 3( - % $ %(%%( + ! ' ' (% $ & $ ( - % - % ( ( xr68c681 6 ( ' ' (% ( - % ((g $ $ ++ ' %(%%( + ' ' (% (% + (% $ ( figure 24 $ figure 26 mr2n[3:0] - stop bit length (% ( +( $ - % $ ( + % (% $ $ ' %( $ ' ' ( $ ( + ./ ( ( $ ./ ( ( %" ( ( ' % + ./ (% ' - $ + ' ' - % + /" @ $ < (% 6 ( ' ' " % ( $ ( ' - $ + ./ ( ( % #+ ! ! ' '3 (% - $ + %( ' '3 5 " m1n j % '% % ( $ ( + ( ( $ m1n j % '% $ ( + ( ( % + %(%%( ' ( & ' '3% + 3 ' $(( ' + +( % % ( (%" ( ( + % $ (& ( (% % $ - $ %% + - $ %( $ % ( - #+ ' ( $ % % h 3i h 2 i 2 (% +-- $ ( % -(% g.4 status register, srn %% -(% ($ % % ( %% 9 $ 9 ' ( $ %( # %" % '( &k $ % % ($ , ( % + c(& + ' ( + $ & ' ( # %% ( $(' % % + ( $ %&% % $ % , ' '3 $ % (+ %( (% & $. (% $& + $ + , # %% ( $(' % % ( $(' 9 % ' ' " (' (% (( - $ & , " (% + $ ( ' + ' (( - & ' ' % ( %( $ ' ( # %% ( $(' % ' $ ( ( + %% -(% ( + %% -(% % % + & $ ' ( % ( + + % -(% $ $(%'%%( + ' ( + %4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received break framing error parity error overrun error txemt txrdy ffull rxrdy j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % table 19. the bit format of the status register?s sra and srb srn[7] received break (% ( ( $(' % g ' ' + - $ ' ' - % ' ( $ ( % ( & %( - # %(( (% ''( $ 3 (% ' ( $ $$(( %+ % ( # ( (( $ ( 5 ( % 3( - % + % + ( ( (% (% $ +( $ % %'' %%( $- % + ( ! ! ' '3 a (% ( (% % " ' f% h9 802 #8 *2 7 i ( ( # (% % ( ( # (% % % $ + 3 ' $(( " % $ +( $ " (% $ ' $ ' (f% 3 $ ' -(' ' $ ' 3% -( ( ($$ + ' ' 9 " 3 % %(% ( $ + ! ' ' ( ( $ + ( $ ' $ #+ $ + ' % % h ' i $ " (% ( & ( % ' ' + 9 (% ( ( ' $ (+ 5 ( (% - -(' h (- i " ( ! ' ' #+ h2 i $ % % h* '3i $ " (% (" ' % ( ( %% $ ( h22 2 i ' $ % ( 3 $ % % table 2 srn[6] framing error ( - ' ( + ' ' (%" $ & %% '( $ (& (" ' ( ( ' '3 + h 3i ' $(( ( ( + ( - % $ (& ( (% h 3i ' $(( (% , ( #+ ' ( $ % xr68c681 61 $ ' h 3i (% ( " ( (% -- $ h (- i +--( - '' ' + 2 2 #+ $ % % h ' i $ " (% ( & ( % ' ' + 9 #+ (% ( (% % + -( ' ' " ( ( ' $ (+ , ( (% & $ ' $ ( ! ' ' #+ h2 i $ % % h* '3i $ " (% (" ' % ( ( %% $ ( h22 2 i ' $ % ( 3 $ % % table 2 , % (+ $ (% h* '3i (% (" ( %% -(% ( ( % " + %% c ' ' %" ( $ $ + ' $(( + % ' ( $ ' ' %" ( h22 2 i ' $ % ( 3 $ srn[5] parity error (% ( (% % ha#9 , #ei h 2 , #ei $ % - $ $ (+ ' % $( - ' ' ( $ # % ' ( $ ( ( ' ' (& #+ $ % % h ' i $ " (% ( & ( % ' ' + 9 #+ (% ( (% % + -( ' ' " ( ( ' $ (+ ' ( $ (& (% ' ' ( ! ' ' #+ h2 i $ % % h* '3i $ " (% (" ' % ( ( %% $ ( h22 2 i ' $ % ( 3 $ % % table 2 , % (+ $ (% h* '3i (% (" ( %% -(% ( ( % " + %% c ' ' %" ( $ $ + ' $(( + % ' ( $ ' ' %" ( h22 2 i ' $ % ( 3 $ srn[4] overrun error #+ % " (% ( ( $(' % ' ' % ( ' ( $ $ % # (% % ' ( + ' ' # (% + $ ' ' (% $& ( (( - + & # %(( a (% '' %" ' ' ( (% ( , % " (3 %% -(% (% + 2 ( - 2 " ,2 , (& 2 $ * ' ( $ * 3" 2 2 ( $(' (% &% +-- $ h* '3i $ %(% 2 ' $(( (% +-- $ ' ' ' ' %(%" $ & ' $ h22 2 i ' $ (% ( 3 $ srn[3] transmitter empty (txemt) (% ( (% % %( $ % # (% % + %(%%( + % % ( + ' ' $ (+ (% ' ' ( 9 (( - %(%%( (% ( (% ' $ %( (% $(% $" , ( % ' ' 9 srn[2] transmitter ready (txrdy) (% (" % " ( $(' % 9 (% & $ $& '' ' ' + , ( (% ' $ , ( % ' ' 9" $ (% % ' ' (% %+ $ 5e (% % %( (% ( ((& $ $ (% % %( (% $(% $ ' % $ $ ( 9 ( %( (% $(% $ ( %( $ srn[1] fifo full (ffull) (% ( (% % ' ' (% %+ $ + 9 $ %+ '% % ( ' + ( " # %(( % ''( $ # (% % , $% 9 #+ ' ' (% (( - ( '% # (% +" :: ( % , $% 9 srn[0] receiver ready (rxrdy) (% ( ( $(' % % ' ' % ' ( $ $ (% (( - ( # $ & , # (% % ' ' (% %+ $ + 9 $ (% ' $ ( , $% % ' ' ' & % $ ( # , % % + ' $(( % +-- $ & %% -(% ' % - $ - ( c % , 9 " % ' $(( % +-- $ & %% -(% ' - $ - ( % ' $(( % (% $ 4 m/n ( - 2 m6n , (& 2 m=n 2 + " (+ %&% ' '3( - (% & $" % (% ' $ $ ($ ' ' ' & ' '3( - %% -(% xr68c681 6= h. special modes of operation h.1 rts/cts handshaking ' - $ % . $% 3( -" % % + $ + ' ( $ (' % (% % '( $ %' ( % ( % % % ( ( ( - . 9 $% 3( - '(+('&" % ( % 4 ' ( $ . 9 $% 3( - %( $ . 9 $% 3( - h.1.1 receiver-controlled rts/cts handshaking # (% $ " ' ( % ((& ('& - %(( - $ (' '(+('&" (% $ % ' ( - %(- (+ (% 9 (% +k $" (% &" & ++ '( ( ( - ' ( % figure 23 % % $(- + ! (% ( - ( + ' ( ' $ ' +(- ( :: #, , figure 23. block diagram and timing sequence of two duarts connected in the receiver-rts controlled configuration. 5 5* receiving device transmitting device 5 5* * * , :: 5 #, ,= , xr68c681 66 figure 23 % % $ (' %" $ h ' (( - (' i $ $ h %(( - (' i (% ! (- % +' h ' (( - (' i % %( $ h %(( - (' i % ' ( " (% ! " (% %( - ' + h ' (( - (' i $ ' * + h %(( - (' i ! % % ( %%( h ' (( - (' i % - $ %' m@n j '' $( - section g.3 " (% %% ( - ( - h ' (( - (' i + ' ( ' $$(( &" h %(( - (' i % - $ %' *m=n j '' $( - section g.3 " %( + ' * + h %(( - (' i % - $ $ * ( ' # (% ! " h ' (( - (' i ' % %(- (% %(- (% + $ $( '& ( * ( + %(( - $ (' #+ 9 + h ' (( - (' i (% + % $ (' $ & :: ( - -(' h (- i" ( ('& - $ & ( + ' ( ' $ + % % c &" ' * %( + h %(( - (' i ( (% * ( - $ $ ( ( $ %( & $ 5 + h ' (( - (' i #+ , $% h %i 9 + ' (( - $ (' " 9 ( - +" $ :: ( $(' ( -- +% # (% '% " :: ( $(' (% ' ' $ % ( + , # % % :: --( - +% " , $ ( (% h -( $- i + :: % ( c % , $ % (' (% h# i & h (( -i m@""n j m" " " " " " " n $$ %% 2 / (% '( ! ' % h2 , , 8i $ '% % ,mn -- h (- i $ ( , -- h i % c &" (% %% $ a( + h ' (( - (' i ( - %% $ ( + h %(( - (' i (% %% $ % " $ $ %(%%( + h %(( - (' i h ' (( - (' i (% ( $ figure 23 % % 5 ( ' (( - $ + % %% $ 9 " ( (% ! " (% & ' ( $ ' ' '% % 9 + h ' (( - (' i + :: ( $(' %% (% %% $ $ + h ' (( - (' i (% ('& - $ ( ' ( ' %(- + " %(%%( + ' * + %(( - $ (' (%" ' -( " ( (( $ figure 24 % % + $(- (% ( - - ( ' $ % $ ( ( ( - ' ( ' $ . $% 3( - $ xr68c681 6/ figure 24. a flow diagram depicting an algorithm that could be used to apply the receiver-controlled rts/cts handshaking mode ' (( - (' m@n j %(( - (' *m@n j 2 a ( ) $$ %% 2 (% ( 3 % h2 , , *# 8i $ % % , ( " , -(' hi #% :: %% $q 8 (% ('& 8 - $ & ' ( $ '( e2 #% :: 8 - $q 8 e2 h.1.2 transmitter-controlled rts/cts handshaking # (% $ " %( % ((& - ' (( - (' '(+('&" (% $ % %( - %(- " ( ( $ + &( - (% 9 $ xr68c681 6@ txrdy_a figure 25. block diagram and timing sequence of two duarts connected in the transmitter-rts controlled configuration. rtsa rxda ctsa rtsa (op0) ctsa (ip0) txda ip2 (rts-in) op3 (cts-out) rxdb transmitting device receiving device txrdy_a to cpu (op7) figure 25 % % $ (' %" $ h %(( - (' i $ " h ' (( - (' i (% ! % % ( %%( h %( (' i % - $ %' m6n j (' %% ( - ( - h %(( - (' i + %( (% ! + %% % h %(( - (' i % - $ %' m=n j '' $( - section g.3 " %( + ' + h %(( - (' i % - $ $ ( ' # '% + h ' (( - (' i" #, ( % - $ - h# , - + i ( c % , +( + ( % (' ( % (% ( %' (+ #, ( ' - $ #,mn j " , $ h ( i m@"" n j m" " " " " " " n $$ %% 2 / # (% % " ( % (' ( $ ( 3 h2 , , *# 8i" $ ( ' %% -- ,m1n -(' h (- i $ ( " ,1" -(' h i (% $" ( " %% ( + h %(( - (' i $ ( %( $ h ' (( - (' i ' ' %( % ( $ (% 9 $ + $" ( ( - " ( h %( i + a + h %(( - (' i (% -- $ h (- i" #, ( (% % -- $ h (- i" & - ( - h# - + i ( c % , a( #,mn j " (3 & ( % (' ( $ ha ( i m@"" n j m" " " " " " " n $$ %% / # (% % " # % (' ( $ ( 3 h:2 , , *# 8i" $ ( ' %% -- ,1 h (- i (% $ ( - ( + h %(( - (' i $ ( (( %(%%( + $ + ' + h %(( - (' i figure 26 % % (- (' $ ('% - ( ' $ % $ ( %( ' . $% 3( - $ , % % $ $ '3% ( '' ' % ( ( h ' (( - (' i a % ha ( i '3% ( ( ( ( h %(( - (' i xr68c681 6< 2 a ( 9 $$ %% 2 %(%%( (% ( $ #8, # 22 h:ai 00:2 ,1 d ,#8 q #, j q 8 (% ('& 8 - $ & ' ( $ '( , -- % h9(- i a ( < $$ %% 2 8 figure 26. a flow diagram depicting an algorithm that could be used to realize the transmitter-controlled rts/cts handshaking mode #% 52 %% $ #% 5e 8 - $q 0 h# , - + i # #, ( ' (( - (' #% 00:2 ,1 d ,#8 h9#09i a ( < $$ %% e % e % 8 e % 8 #8, # 820 2 %(%%( (% $(% $ h.2 multi-drop (8051 9 bit) mode 2' % ( ' + ' ' +(- $ ( 3 $ % + + ( $ ( ' %% ('( % (% % '( ( +( % % ' ' + ( $ $ $ &" + '( $ ' $ + ( - ( ( $ $ h.2.1 concept of multi-drop mode (% $ (% ' ( ( % ( h8( ( $ i + <6 +(& (' ' % # (% $ + ( h% %( i" ' ' $ !( + 6/ % %( % (% %%( " % $ (' $ ( figure 27 xr68c681 6 5 figure 27. an illustration depicting the concept of multi-drop mode 5 5 5 5 % (' (' % . :* * < *( ' $$ %%. *( figure 28. bit format of character data being transmitted in the multi-drop mode h% ( i ' (' % h ( %i & %(( - ' ' &('& & ( h $$ %%.i ( +- $ $ $ + ' ' (% &('& %% ( ( (% + $ ( - %( $ + & ' ' & " % % $ ( figure 28 a h% ( i % %( '3 + $ + % % %" ( +( % % $% $$ %% & ($ (+( % h - i $$ %% & $(++ % + $ & ( ( ( (% hi ( $$ %% & $ hi ( $ & $$ %% & " " ( % h %i % ' ' !( ' ( $ & % (+ ( ( $(($ % $ (' (% ( - $$ %% $ ' ( + $$ %% $ % ( $ $ ( + ' ( + $ & % + % % % $$ %% $ ( % ( ' ( % $(% $" $ ( ' ( (- $ & % + % & ( ( $ -( ! $$ %% & (% %( $ & h% (' i h.2.2 duart multi-drop operation -( ' ( ( (% - $ ( ( $ $ & % ( - m=41n j h" i # (% $ " %( $ ' ' ' %(%% + (" - $ + $ (%" $$ %%. . +- (k $ - $ , ( - . j ( $(' % ' ' (% $" ( . j ($ (+( % ( % $$ %% transmitter operation during multi-drop mode % ., ' % % + %( $ ' ' & - ( - mn + ' ( $( - $ (% ( 9 ( - mn j hi %% ( . j hi $ % ( - mn j hi %% ( . j hi figure 29 % % ' $ + $(- + %(( - ' ' % $$ %% " ( ( ( $ $ xr68c681 / figure 29. a flow diagram depicting a procedure that can be used to transmit characters in the multi-drop mode. # 3 h22 ,#82i ' $ a ( ! ( $ -(% . *( hi a ( !!!!!!! -(% %( $$ %% ' (' a ( ' 9 # 3 h22 ,#82i ' $ a ( ! ( $ -(% . *( hi a ( !!!!!!! -(% %( ' (' a ( ' 9 ' % a ( '( (' q 8 e % receiver operation during multi-drop mode a ' % - $ ( ( $ $ " $ ' ( % $(% $ &(' ' +(- ( " ' ( ( $ ' ' ( 9 $ % 5e ( $(' $. ( (+ . ( (% hi $$ %% +- 9 " ' ' ( $(%' $ $ (+ (% . ( (% hi +- + " ( % % 5e ( $(' " , % $ $ ' ( $ ' ' $ $ ( (+ $$ %% ( % % ' % + , #+ $$ %% % $ ' " ( $('( - ( (% h - i" , % $ ' ( " ( ( + %% c '3% + $ ' ' ( % $ ' ( % ( $ ( ' %% $ % ( ( ' ( $ ' ' % '' %%( , & $( - 9 % + . +- ( (% ( m6n" %% -(% ( & % $ ( $(' h, (& 2 i + " ( ' l '( ( ' ( ' ' ' " , % $ ' ( ( m6n ( $ (+& ( (% hi ' ' % ' h - , i $ '% $$ %% ' ' " m6n jhi" ( % $ ' (% $$ %% ( (% #+ xr68c681 / $$ %% % $ ' " (% , (% ( $ $ '(( + ! '3 + $" $ % $ $(% ' ( figure 30 % % + $(- $ ('( - ' $ $ ' $ + $( - ' ( $ ' ' % ( ( ( $ $ figure 30. a flow diagram depicting a procedure that can be used to receive characters in the multi-drop mode. ' ( (% (% $ (% $ $ ( ( $ m=41n j m" n l ' ' ' ( ( % (% $ $ ( $$ %% ' + 9 9% 5e # $(' %% $ q 8 e % 8 2 ' ( a ( ! ( $ -(% $ ( ' + 9 '3 m6n % 8 & ' ( $ $$ %% ' , $$ %% q #% 8 ' ' m6n j q e % e % 8 h.3 standby mode & ' $ ( % $& $ ' % (% ( (% c( $ % " ( ( h #;2 ,2 #8i $ h2 8*e 2i ' $ (%% $ ( ' ' $ -(% $(% % ' '3% $ (' !' + ' &% %'( " (' %(- (+(' & $' % ( - ' # % $& $ " & + '( % (' ( ' ( ' '& $( - ( " (( - $ ( 3( - h2 #;2 2i ' $ " % ( 3 $ ( ' ' $ -(% " % % $ (' ( ( ( 6 % % ( - %( % $ ' ( % $ (( - ( # # %3 -(% + - ( - ( % $& $ " (% ' $ $ & % ( % ( % + ( - - $ ' ( % $ - $ + h2 #;2 2i ' $" %( ' -(% ' % - $ ( % $ ( - % $& $ '( ( ' % % $ ( $ % xr68c681 / i. programming ( + (% - $ & (( - ' $% ( ( -(% %" ( ( + $'3 (% ($ $ & %% -(% % (' ' $ & , -(% $$ %%( - (% % ( table 1 $ % ' % ' % + " #" #" ," $ , -(% % $ ( (((g % #; / ( - ( " ' % $ ! '(% $ (+ ' % + ' -(% % ' - $" %( ' ' ( ' - % & % ( ( ( ! " ' -( - + (% ' ' ( $ (% ( - ' ( $ & % ( ' ( + % ' ' # - " ' - % -(% % (' ' ' ( %( ( % $ $ & ( %( ' ( $(% $" $ ' ( ' - % % $ $ & . (% % $ $ " ' $" ' '3 % '" $ %% -(% % $(' $ + ' ' ($ ( $ $ ( table 10 % (g % ( %%(- % + ' -(% bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx rts control rx int select error mode parity mode select parity select number of bits/char. j8 je % j5e j :: j j * '3 j a( , (& j ' , (& j 8 , (& j ( $ j 2 j $$ j 6 j / j @ j < table 20. mode registers 1: mr1a, mr1b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 channel mode tx rts control cts enable tx stop bit length j 8 j 2' j : ' : j : j8 je % j8 je % j 6/1 j /6 j /<< 1 j @6 = j <1 6 j <@6 / j 1< @ j < j 6/1 j /6 j /<< * j @6 j <1 j <@6 2 j 1< j table 21. mode register 2: mr2a, mr2b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ' ( '3 ' %( '3 ' table 6 table 6 table 22. clock select registers: csra, csrb xr68c681 /1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miscellaneous commands enable / disable transmitter enable / disable receiver ! ( section b.2 j 8 - j 2 ! j (% ! j 8 ;($ 8 % j 8 - j 2 ! j (% ! j 8 ;($ 8 % table 23. command registers: cra, crb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received break framing error parity error overrun error txemt txrdy ffull rxrdy j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % table 24. status registers: sra, srb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op7 op6 op5 op4 op3 op2 j,m@n j5e* j,m/n j5e j,m6n j5e. ::* j,m=n j5e. :: j ,m1n j . p j 5* 5 j 5* 5 j ,mn j 5 /5 j 5 5 j 5 5 table 25. output port configuration register: opcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 brg set select counter/timer #1 mode and source delta ip3 interrupt delta ip2 interrupt delta ip1 interrupt delta ip0 interrupt j j table 4 j j8 j j8 j j8 j j8 table 26. auxilliary control register: acr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 delta ip3 delta ip2 delta ip1 delta ip0 ip3 ip2 ip1 ip0 j8 je % j8 je % j8 je % j8 je % j : j 9(- j : j 9(- j : j 9(- j : j 9(- table 27. input port configuration register , ipcr xr68c681 /= bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter #1 ready delta break a rxrdy/ ffulla txrdya j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % j8 je % table 28. interrupt status register, isr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter #1 ready delta break a rxrdy/ ffulla txrdya j++ j j++ j j++ j j++ j j++ j j++ j j++ j j++ j table 29. interrupt mask register, imr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 .6 .= .1 . . . . .< table 30. counter/timer upper byte register, ctur bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 .@ ./ .6 .= .1 . . . table 31. counter/timer lower byte register, ctlr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 #;@ #;/ #;6 #;= #;1 #; #; #; table 32. interrupt vector register: ivr xr68c681 /6 xr68c681 // j. timing diagrams =; figure 31. input and output levels for timing measurements ; <; % : % ; <; note: ac testing inputs are driven at 0.4v for a logic ?0? and 2.4v for a logic ?1? except for -40 to 85 c and -55 to 125 c, logic ?1? shall be 2.6v. timing measurements are made at 0.8v for a logic ?0? and 2.0v for a logic ?1?. 22 2 figure 32. reset timing xr68c681 /@ a = .a @ 7 9 a a9 : 9 5.:7 figure 33. xr68c681 read cycle timing xr68c681 /< 5.:7 a a figure 34. xr68c681 write cycle timing = .a @ 7 : 9 a9 9 xr68c681 / figure 35. xr68c681 interrupt cycle timing #8 7 # 7 5.:7 @ ;2 9 : xr68c681 @ figure 36. port timing .a #, #,6 , ,@ , ,9 : 82a , figure 37. interrupt timing .a #8 # xr68c681 @ :7 5 figure 38. clock timing 5/</< :7 5 5.:7 . :7 5 5 5 5 1/ &% 4 ? & o 6 4 ? & o 6 4 4 xr68c681 @ 5 # figure 39. transmitter timing 5 5 5 *( ( / '3% 5 5 5 # 5 5 59 figure 40. receiver timing xr68c681 @1 44 lead plastic leaded chip carrier (plcc) rev. 1.00 d d a a 1 d d 1 d 3 /6 < = =6@ 16 rrr 6 rrr * 1 11 61 * / 1 // < < 1 1 /<6 /6 @= @/6 /6 /6/ /6 /// 6 /1 = / 1 6 & @ & 6 * @ * 9 = 6/ @ = 9 = =< @ 6 =6 /= = symbol min max min max inches millimeters b a 2 b 1 e ( - , d 2 == note: the control dimension is the inch column d 3 45 xh2 45 xh1 c r xr68c681 @= d b e b 1 40 lead ceramic dual-in-line (600 mil cdip) rev. 1.00 = c e 1 l a 1 seating plane base plane a 6 6= 6@ 6 @6 1< * = / 1/ // * =6 /6 = /6 ' < < =/ 666 61 2 66 / 1@ 6= 2 / * 6= * * 6= * : 6 1< 6< 6 6 symbol min max min max inches millimeters e note: the control dimension is the inch column xr68c681 @6 8#2 25 ( % % (- 3 ' - % $'% ' ( $ ( (% ('( ( $ ( $ %(- " + ' (((& 25 ( %% % % %(((& + % + & '( '(% $ %' ( $ ( " ' &% (' % $ & (- " $ 3 % % ( '( '(% + + ( + ( - % $ %' $ % ' ( $ ( & + (% ( % % $ & & $ $( - % f% % '(+(' ('( a ( ( + ( ( (% ('( % ' +& ' '3 $k % %(((&" " (% %% $ + ( '' '( % 25 ( $ % ' $ % + & + (% $'% ( (+ % ('( % +( + '( + $' ' % & ! ' $ '% +( + (+ % %&% %(- (+(' & ++ ' (% %+ & ++ '( %% , $'% (g $ + % ( %' ('( % %% 25 ( ' ( %" ( (( -" %% ' % (% %(%+'( 4 (%3 + ( l & $- % ( ((g $k % %% % %' (%3%k ' ( (((& + 25 ( (% $ c & ' $ $ '( ' % ' % & (- 25 ( % $'( " ( " ( ( ( ' % + 25 ( (% (( $ |
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